Remove redundant 'artiq.gateware' from module names
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README.md
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README.md
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@ -5,19 +5,18 @@ Formally verified implementation of the ARTIQ RTIO core in nMigen
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## Progress
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- [ ] Implement the core in nMigen
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- - [ ] `artiq.gateware.rtio.core`
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- - [ ] `misoc.interconnect.csr`
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- - [ ] `artiq.gateware.rtio.cri`
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- - [x] `artiq.gateware.rtio.rtlink`
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- - [x] `artiq.gateware.rtio.channel`
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- - [ ] `artiq.gateware.rtio.sed.core`
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- - [x] `artiq.gateware.rtio.sed.layouts`
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- - [ ] `artiq.gateware.rtio.sed.lane_distributor`
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- - [ ] `artiq.gateware.rtio.sed.fifos`
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- - [ ] `artiq.gateware.rtio.sed.gates`
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- - [ ] `artiq.gateware.rtio.sed.output_driver`
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- - [ ] `artiq.gateware.rtio.sed.output_network`
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- - [ ] `artiq.gateware.rtio.input_collector`
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- - [ ] `rtio.core`
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- - [ ] `rtio.cri`
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- - [x] `rtio.rtlink`
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- - [x] `rtio.channel`
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- - [ ] `rtio.sed.core`
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- - [x] `rtio.sed.layouts`
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- - [ ] `rtio.sed.lane_distributor`
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- - [ ] `rtio.sed.fifos`
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- - [ ] `rtio.sed.gates`
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- - [ ] `rtio.sed.output_driver`
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- - [ ] `rtio.sed.output_network`
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- - [ ] `rtio.input_collector`
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- [ ] Add suitable assertions for verification (BMC / unbounded proof?)
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## License
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@ -1,6 +1,6 @@
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import warnings
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from artiq.gateware.rtio import rtlink
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from rtio import rtlink
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class Channel:
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@ -2,7 +2,7 @@ from nmigen import *
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from nmigen.utils import *
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from nmigen.hdl.rec import *
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from artiq.gateware.rtio import rtlink
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from rtio import rtlink
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def fifo_payload(channels):
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