Increase BMC depth for sorting network assertions
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036c91539b
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@ -119,12 +119,10 @@ class OutputNetwork(Elaboratable):
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f_past_valid = Signal()
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m.d.sync += f_past_valid.eq(1)
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# TODO: assert outputs is a permutation of inputs
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# Channel numbers for outputs are sorted in increasing order
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# Valid nodes always come first in outputs
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with m.If(f_past_valid):
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# TODO: Get the below (bogus) assertion to fail
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m.d.comb += Assert(self.output[7].payload.channel == 0)
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for i in range(lane_count - 1):
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m.d.comb += Assert(self.output[i].valid | ~self.output[i + 1].valid) # TODO: Figure out why this is failing
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def elaborate(self, platform):
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return self.m
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@ -12,7 +12,7 @@ class OutputNetworkTestCase(FHDLTestCase):
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# Bounded model check
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self.assertFormal(
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OutputNetwork(16, 2, [("data", 32), ("channel", 3)], fv_mode=True),
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mode="bmc", depth=10)
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mode="bmc", depth=40)
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# TODO: unbounded proof
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OutputNetworkTestCase().verify()
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