Skip assertions for configurable no. of clock cycles

rtio/sed/output_network.py

@@ -119,8 +119,16 @@ class OutputNetwork(Elaboratable):
             f_past_valid = Signal()
             m.d.sync += f_past_valid.eq(1)
 
+            # Skip assertions for the first 10 time steps
+            counter = Signal(4)
+            m.d.sync += counter.eq(counter + 1)
+            with m.If(counter >= 10):
+                m.d.sync += counter.eq(counter)
+            f_past10_valid = Signal()
+            m.d.comb += f_past10_valid.eq(counter >= 10)
+
             # Valid nodes always come first in outputs
-            with m.If(f_past_valid):
+            with m.If(f_past10_valid):
                 for i in range(lane_count - 1):
                     m.d.comb += Assert(self.output[i].valid | ~self.output[i + 1].valid) # TODO: Figure out why this is failing