Add failing trace and trace analysis
This commit is contained in:
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@ -2,6 +2,14 @@
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Formally verified implementation of the ARTIQ RTIO core in nMigen
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## File Synopsis
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- `LICENSE`: License terms (LGPLv3+) for this project
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- `README.md`: this document
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- `shell.nix`: Nix file for setting up the environment for this project
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- `rtio`: RTIO core in nMigen
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- `traces`: History of traces for debugging
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## Progress
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- Devise a suitable migration strategy for `artiq.gateware.rtio` from Migen to nMigen
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@ -119,18 +119,9 @@ class OutputNetwork(Elaboratable):
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f_past_valid = Signal()
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m.d.sync += f_past_valid.eq(1)
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# Skip assertions for the first 10 time steps
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counter = Signal(4)
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m.d.sync += counter.eq(counter + 1)
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with m.If(counter >= 10):
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m.d.sync += counter.eq(counter)
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f_past10_valid = Signal()
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m.d.comb += f_past10_valid.eq(counter >= 10)
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# Valid nodes always come first in outputs
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with m.If(f_past10_valid):
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for i in range(lane_count - 1):
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m.d.comb += Assert(self.output[i].valid | ~self.output[i + 1].valid) # TODO: Figure out why this is failing
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for i in range(lane_count - 1):
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m.d.comb += Assert(self.output[i].valid | ~self.output[i + 1].valid) # TODO: Figure out why this is failing
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def elaborate(self, platform):
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return self.m
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92
traces/0/NOTES.md
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92
traces/0/NOTES.md
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@ -0,0 +1,92 @@
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# Dissecting the failing trace
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N.B. The value of a node `n` is given by `Cat(n.payload.channel, ~n.valid)`
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## Cycle \#0 (MATCH)
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Events: N/A
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Values:
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- node0 value: `0010`
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- node0 valid: `1`
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- node0 channel: `010`
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- node0 sequence: `00`
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- node1 value: `0000`
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- node1 valid: `1`
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- node1 channel: `000`
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- node1 sequence: `00`
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- node2 value: `0001`
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- node2 valid: `1`
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- node2 channel: `001`
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- node2 sequence: `11`
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- node3 value: `0000`
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- node3 valid: `1`
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- node3 channel: `000`
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- node3 sequence: `01`
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To compare:
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- node0 and node1
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- node2 and node3
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## Cycle \#1 (MATCH)
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Events: N/A
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Values:
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- node0 value: `0000`
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- node0 valid: `1`
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- node0 channel: `000`
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- node0 sequence: `00`
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- node1 value: `0010`
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- node1 valid: `1`
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- node1 channel: `010`
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- node1 sequence: `00`
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- node2 value: `0000`
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- node2 valid: `1`
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- node2 channel: `000`
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- node2 sequence: `01`
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- node3 value: `0001`
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- node3 valid: `1`
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- node3 channel: `001`
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- node3 sequence: `11`
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To compare:
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- node0 and node2
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- node1 and node3
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## Cycle \#2 (NOMATCH - see trace for diff)
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Events:
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- A replacement occurred when comparing node0 and node2
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Values:
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- node0 value: `0000`
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- node0 valid: `1`
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- node0 channel: `000`
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- node0 sequence: `01`
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- node1 value: `0001`
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- node1 valid: `1`
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- node1 channel: `001`
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- node1 sequence: `11`
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- node2 value: `1000`
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- node2 valid: `0`
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- node2 channel: `000`
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- node2 sequence: `00`
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- node3 value: `0010`
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- node3 valid: `1`
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- node3 channel: `010`
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- node3 sequence: `00`
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To compare:
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- node1 and node2
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# Cycle \#3
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TODO: fill this in after figuring out why my prediction for Cycle \#2 fails to match generated trace
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786
traces/0/trace.vcd
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786
traces/0/trace.vcd
Normal file
@ -0,0 +1,786 @@
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$version Generated by Yosys-SMTBMC $end
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$timescale 1ns $end
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$var integer 32 t smt_step $end
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$var event 1 ! smt_clock $end
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$scope module top $end
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$var wire 1 n0 clk $end
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$var wire 1 n1 f_past_valid $end
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$var wire 1 n2 nondata_difference $end
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$var wire 1 n3 nondata_difference$127 $end
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$var wire 1 n4 nondata_replace_occured $end
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$var wire 1 n5 nondata_replace_occured$22 $end
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$var wire 1 n6 nondata_replace_occured$40 $end
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$var wire 1 n7 nondata_replace_occured$58 $end
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$var wire 3 n8 payload__channel $end
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$var wire 3 n9 payload__channel$28 $end
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$var wire 3 n10 payload__channel$46 $end
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$var wire 3 n11 payload__channel$64 $end
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$var wire 32 n12 payload__data $end
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$var wire 32 n13 payload__data$25 $end
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$var wire 32 n14 payload__data$43 $end
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$var wire 32 n15 payload__data$61 $end
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$var wire 1 n16 rec__nondata_replace_occured $end
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$var wire 1 n17 rec__nondata_replace_occured$133 $end
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$var wire 1 n18 rec__nondata_replace_occured$133$next $end
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$var wire 1 n19 rec__nondata_replace_occured$165 $end
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$var wire 1 n20 rec__nondata_replace_occured$165$next $end
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$var wire 1 n21 rec__nondata_replace_occured$200 $end
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$var wire 1 n22 rec__nondata_replace_occured$232 $end
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$var wire 1 n23 rec__nondata_replace_occured$232$next $end
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$var wire 1 n24 rec__nondata_replace_occured$267 $end
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$var wire 1 n25 rec__nondata_replace_occured$299 $end
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$var wire 1 n26 rec__nondata_replace_occured$334 $end
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$var wire 1 n27 rec__nondata_replace_occured$366 $end
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$var wire 1 n28 rec__nondata_replace_occured$398 $end
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$var wire 1 n29 rec__nondata_replace_occured$398$next $end
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$var wire 1 n30 rec__nondata_replace_occured$404 $end
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$var wire 1 n31 rec__nondata_replace_occured$404$next $end
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$var wire 1 n32 rec__nondata_replace_occured$98 $end
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$var wire 1 n33 rec__nondata_replace_occured$98$next $end
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$var wire 1 n34 rec__nondata_replace_occured$next $end
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$var wire 3 n35 rec__payload__channel $end
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$var wire 3 n36 rec__payload__channel$100 $end
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$var wire 3 n37 rec__payload__channel$100$next $end
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$var wire 3 n38 rec__payload__channel$135 $end
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$var wire 3 n39 rec__payload__channel$135$next $end
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$var wire 3 n40 rec__payload__channel$167 $end
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$var wire 3 n41 rec__payload__channel$167$next $end
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$var wire 3 n42 rec__payload__channel$202 $end
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$var wire 3 n43 rec__payload__channel$234 $end
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$var wire 3 n44 rec__payload__channel$234$next $end
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$var wire 3 n45 rec__payload__channel$269 $end
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$var wire 3 n46 rec__payload__channel$269$next $end
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$var wire 3 n47 rec__payload__channel$301 $end
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$var wire 3 n48 rec__payload__channel$336 $end
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$var wire 3 n49 rec__payload__channel$368 $end
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$var wire 3 n50 rec__payload__channel$400 $end
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$var wire 3 n51 rec__payload__channel$400$next $end
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$var wire 3 n52 rec__payload__channel$406 $end
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$var wire 3 n53 rec__payload__channel$406$next $end
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$var wire 3 n54 rec__payload__channel$next $end
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$var wire 32 n55 rec__payload__data $end
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$var wire 32 n56 rec__payload__data$134 $end
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$var wire 32 n57 rec__payload__data$134$next $end
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$var wire 32 n58 rec__payload__data$166 $end
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$var wire 32 n59 rec__payload__data$166$next $end
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$var wire 32 n60 rec__payload__data$201 $end
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$var wire 32 n61 rec__payload__data$233 $end
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$var wire 32 n62 rec__payload__data$233$next $end
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$var wire 32 n63 rec__payload__data$268 $end
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$var wire 32 n64 rec__payload__data$268$next $end
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$var wire 32 n65 rec__payload__data$300 $end
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$var wire 32 n66 rec__payload__data$335 $end
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$var wire 32 n67 rec__payload__data$367 $end
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$var wire 32 n68 rec__payload__data$399 $end
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$var wire 32 n69 rec__payload__data$399$next $end
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$var wire 32 n70 rec__payload__data$405 $end
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$var wire 32 n71 rec__payload__data$405$next $end
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$var wire 32 n72 rec__payload__data$99 $end
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$var wire 32 n73 rec__payload__data$99$next $end
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$var wire 32 n74 rec__payload__data$next $end
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$var wire 1 n75 rec__replace_occured $end
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$var wire 1 n76 rec__replace_occured$132 $end
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$var wire 1 n77 rec__replace_occured$132$next $end
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$var wire 1 n78 rec__replace_occured$164 $end
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$var wire 1 n79 rec__replace_occured$164$next $end
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$var wire 1 n80 rec__replace_occured$199 $end
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$var wire 1 n81 rec__replace_occured$231 $end
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$var wire 1 n82 rec__replace_occured$231$next $end
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$var wire 1 n83 rec__replace_occured$266 $end
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$var wire 1 n84 rec__replace_occured$298 $end
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$var wire 1 n85 rec__replace_occured$333 $end
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$var wire 1 n86 rec__replace_occured$365 $end
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$var wire 1 n87 rec__replace_occured$397 $end
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$var wire 1 n88 rec__replace_occured$397$next $end
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$var wire 1 n89 rec__replace_occured$403 $end
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$var wire 1 n90 rec__replace_occured$403$next $end
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$var wire 1 n91 rec__replace_occured$97 $end
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$var wire 1 n92 rec__replace_occured$97$next $end
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$var wire 1 n93 rec__replace_occured$next $end
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$var wire 2 n94 rec__seqn $end
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$var wire 2 n95 rec__seqn$131 $end
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$var wire 2 n96 rec__seqn$131$next $end
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$var wire 2 n97 rec__seqn$163 $end
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$var wire 2 n98 rec__seqn$163$next $end
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$var wire 2 n99 rec__seqn$198 $end
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$var wire 2 n100 rec__seqn$230 $end
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$var wire 2 n101 rec__seqn$230$next $end
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$var wire 2 n102 rec__seqn$265 $end
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$var wire 2 n103 rec__seqn$265$next $end
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$var wire 2 n104 rec__seqn$297 $end
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$var wire 2 n105 rec__seqn$332 $end
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$var wire 2 n106 rec__seqn$364 $end
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$var wire 2 n107 rec__seqn$396 $end
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$var wire 2 n108 rec__seqn$396$next $end
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$var wire 2 n109 rec__seqn$402 $end
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$var wire 2 n110 rec__seqn$402$next $end
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$var wire 2 n111 rec__seqn$96 $end
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$var wire 2 n112 rec__seqn$96$next $end
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$var wire 2 n113 rec__seqn$next $end
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$var wire 1 n114 rec__valid $end
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$var wire 1 n115 rec__valid$130 $end
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$var wire 1 n116 rec__valid$130$next $end
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$var wire 1 n117 rec__valid$162 $end
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$var wire 1 n118 rec__valid$162$next $end
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$var wire 1 n119 rec__valid$197 $end
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$var wire 1 n120 rec__valid$197$next $end
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$var wire 1 n121 rec__valid$229 $end
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$var wire 1 n122 rec__valid$229$next $end
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$var wire 1 n123 rec__valid$264 $end
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$var wire 1 n124 rec__valid$264$next $end
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$var wire 1 n125 rec__valid$296 $end
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$var wire 1 n126 rec__valid$296$next $end
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$var wire 1 n127 rec__valid$331 $end
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$var wire 1 n128 rec__valid$331$next $end
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$var wire 1 n129 rec__valid$363 $end
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$var wire 1 n130 rec__valid$363$next $end
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$var wire 1 n131 rec__valid$395 $end
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$var wire 1 n132 rec__valid$395$next $end
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$var wire 1 n133 rec__valid$401 $end
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$var wire 1 n134 rec__valid$401$next $end
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$var wire 1 n135 rec__valid$95 $end
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$var wire 1 n136 rec__valid$95$next $end
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$var wire 1 n137 rec__valid$next $end
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$var wire 1 n138 replace_occured $end
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$var wire 1 n139 replace_occured$19 $end
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$var wire 1 n140 replace_occured$37 $end
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$var wire 1 n141 replace_occured$55 $end
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$var wire 1 n142 rst $end
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$var wire 2 n143 seqn $end
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$var wire 2 n144 seqn$16 $end
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$var wire 2 n145 seqn$34 $end
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$var wire 2 n146 seqn$52 $end
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$var wire 1 n147 valid $end
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$var wire 1 n148 valid$13 $end
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$var wire 1 n149 valid$31 $end
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$var wire 1 n150 valid$49 $end
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$upscope $end
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$enddefinitions $end
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#0
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1!
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b00000000000000000000000000000000 t
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b1 n0
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b0 n1
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b1 n2
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b1 n3
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b0 n4
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b0 n5
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b0 n6
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b0 n7
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b010 n8
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b000 n9
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b001 n10
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b000 n11
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b00000000000000000000000000000000 n12
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b00000000000000000000000000000000 n13
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b00000000000000000000000000000000 n14
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b00000000000000000000000000000000 n15
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b0 n16
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b0 n17
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b0 n18
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b0 n19
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b0 n20
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b0 n21
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b0 n22
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b0 n23
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b0 n24
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b0 n25
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b0 n26
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b0 n27
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b0 n28
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b0 n29
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b0 n30
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b0 n31
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b0 n32
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b0 n33
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b0 n34
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b000 n35
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b000 n36
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b010 n37
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b000 n38
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b000 n39
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b000 n40
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b001 n41
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b000 n42
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b000 n43
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b000 n44
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b000 n45
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b000 n46
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b000 n47
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b000 n48
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b000 n49
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b000 n50
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b000 n51
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b000 n52
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b000 n53
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b000 n54
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b00000000000000000000000000000000 n55
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b00000000000000000000000000000000 n56
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b00000000000000000000000000000000 n57
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b00000000000000000000000000000000 n58
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b00000000000000000000000000000000 n59
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b00000000000000000000000000000000 n60
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b00000000000000000000000000000000 n61
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b00000000000000000000000000000000 n62
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b00000000000000000000000000000000 n63
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b00000000000000000000000000000000 n64
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b00000000000000000000000000000000 n65
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b00000000000000000000000000000000 n66
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b00000000000000000000000000000000 n67
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b00000000000000000000000000000000 n68
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b00000000000000000000000000000000 n69
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b00000000000000000000000000000000 n70
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b00000000000000000000000000000000 n71
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b00000000000000000000000000000000 n72
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b00000000000000000000000000000000 n73
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b00000000000000000000000000000000 n74
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b0 n75
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b0 n76
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b0 n77
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b0 n78
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b0 n79
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b0 n80
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b0 n81
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b0 n82
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b0 n83
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b0 n84
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b0 n85
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b0 n86
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b0 n87
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b0 n88
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b0 n89
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b0 n90
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b0 n91
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b0 n92
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b0 n93
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b00 n94
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b00 n95
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b01 n96
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b00 n97
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b11 n98
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b00 n99
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b00 n100
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b00 n101
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b00 n102
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b00 n103
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b00 n104
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b00 n105
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b00 n106
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b00 n107
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b00 n108
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b00 n109
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b00 n110
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b00 n111
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b00 n112
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b00 n113
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b0 n114
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b0 n115
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b1 n116
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b0 n117
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b1 n118
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b0 n119
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b0 n120
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b0 n121
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b0 n122
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b0 n123
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b0 n124
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b0 n125
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b0 n126
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b0 n127
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b0 n128
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b0 n129
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b0 n130
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b0 n131
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b0 n132
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b0 n133
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b0 n134
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b0 n135
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b1 n136
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b1 n137
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b0 n138
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b0 n139
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b0 n140
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b0 n141
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b0 n142
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b00 n143
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b00 n144
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b11 n145
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b01 n146
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b1 n147
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b1 n148
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b1 n149
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b1 n150
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#5
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b0 n0
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#10
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1!
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b00000000000000000000000000000001 t
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b1 n0
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b0 n1
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b0 n2
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b0 n3
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b0 n4
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b0 n5
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b0 n6
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b0 n7
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b000 n8
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b000 n9
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b000 n10
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b000 n11
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b00000000000000000000000000000000 n12
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b00000000000000000000000000000000 n13
|
||||
b00000000000000000000000000000000 n14
|
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b00000000000000000000000000000000 n15
|
||||
b0 n16
|
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|
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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|
||||
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||||
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||||
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|
||||
b00000000000000000000000000000000 n55
|
||||
b00000000000000000000000000000000 n56
|
||||
b00000000000000000000000000000000 n57
|
||||
b00000000000000000000000000000000 n58
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||||
b00000000000000000000000000000000 n59
|
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b00000000000000000000000000000000 n60
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b00000000000000000000000000000000 n61
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b00000000000000000000000000000000 n62
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b00000000000000000000000000000000 n63
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b00000000000000000000000000000000 n64
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b00000000000000000000000000000000 n66
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b00000000000000000000000000000000 n67
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b00000000000000000000000000000000 n68
|
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b00000000000000000000000000000000 n69
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b00000000000000000000000000000000 n70
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b00000000000000000000000000000000 n71
|
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b00000000000000000000000000000000 n72
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b00000000000000000000000000000000 n73
|
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b00000000000000000000000000000000 n74
|
||||
b0 n75
|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
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b1 n93
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||||
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||||
b01 n95
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||||
b00 n96
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b11 n97
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||||
b00 n98
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b00 n99
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b00 n100
|
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b00 n101
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||||
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|
||||
#15
|
||||
b0 n0
|
||||
#20
|
||||
1!
|
||||
b00000000000000000000000000000010 t
|
||||
b1 n0
|
||||
b0 n1
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||||
b00000000000000000000000000000000 n12
|
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
b0 n147
|
||||
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|
||||
b0 n149
|
||||
b0 n150
|
||||
#25
|
||||
b0 n0
|
||||
#30
|
||||
1!
|
||||
b00000000000000000000000000000011 t
|
||||
b1 n0
|
||||
b0 n1
|
||||
b0 n2
|
||||
b0 n3
|
||||
b0 n4
|
||||
b0 n5
|
||||
b0 n6
|
||||
b0 n7
|
||||
b000 n8
|
||||
b000 n9
|
||||
b000 n10
|
||||
b000 n11
|
||||
b00000000000000000000000000000000 n12
|
||||
b00000000000000000000000000000000 n13
|
||||
b00000000000000000000000000000000 n14
|
||||
b00000000000000000000000000000000 n15
|
||||
b0 n16
|
||||
b0 n17
|
||||
b0 n18
|
||||
b0 n19
|
||||
b0 n20
|
||||
b0 n21
|
||||
b0 n22
|
||||
b0 n23
|
||||
b0 n24
|
||||
b0 n25
|
||||
b0 n26
|
||||
b0 n27
|
||||
b0 n28
|
||||
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|
||||
b0 n30
|
||||
b0 n31
|
||||
b0 n32
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
b000 n52
|
||||
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|
||||
b000 n54
|
||||
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|
||||
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|
||||
b00000000000000000000000000000000 n57
|
||||
b00000000000000000000000000000000 n58
|
||||
b00000000000000000000000000000000 n59
|
||||
b00000000000000000000000000000000 n60
|
||||
b00000000000000000000000000000000 n61
|
||||
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|
||||
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|
||||
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|
||||
b00000000000000000000000000000000 n65
|
||||
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|
||||
b00000000000000000000000000000000 n67
|
||||
b00000000000000000000000000000000 n68
|
||||
b00000000000000000000000000000000 n69
|
||||
b00000000000000000000000000000000 n70
|
||||
b00000000000000000000000000000000 n71
|
||||
b00000000000000000000000000000000 n72
|
||||
b00000000000000000000000000000000 n73
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
b0 n84
|
||||
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|
||||
b0 n86
|
||||
b0 n87
|
||||
b0 n88
|
||||
b0 n89
|
||||
b0 n90
|
||||
b0 n91
|
||||
b0 n92
|
||||
b1 n93
|
||||
b00 n94
|
||||
b00 n95
|
||||
b00 n96
|
||||
b00 n97
|
||||
b00 n98
|
||||
b00 n99
|
||||
b00 n100
|
||||
b00 n101
|
||||
b00 n102
|
||||
b00 n103
|
||||
b00 n104
|
||||
b00 n105
|
||||
b00 n106
|
||||
b00 n107
|
||||
b00 n108
|
||||
b00 n109
|
||||
b00 n110
|
||||
b00 n111
|
||||
b00 n112
|
||||
b00 n113
|
||||
b0 n114
|
||||
b0 n115
|
||||
b0 n116
|
||||
b0 n117
|
||||
b0 n118
|
||||
b0 n119
|
||||
b0 n120
|
||||
b0 n121
|
||||
b0 n122
|
||||
b0 n123
|
||||
b0 n124
|
||||
b0 n125
|
||||
b0 n126
|
||||
b1 n127
|
||||
b0 n128
|
||||
b0 n129
|
||||
b0 n130
|
||||
b1 n131
|
||||
b0 n132
|
||||
b1 n133
|
||||
b0 n134
|
||||
b0 n135
|
||||
b0 n136
|
||||
b0 n137
|
||||
b0 n138
|
||||
b0 n139
|
||||
b0 n140
|
||||
b0 n141
|
||||
b0 n142
|
||||
b00 n143
|
||||
b00 n144
|
||||
b00 n145
|
||||
b00 n146
|
||||
b0 n147
|
||||
b0 n148
|
||||
b0 n149
|
||||
b0 n150
|
||||
#35
|
||||
b0 n0
|
||||
#40
|
||||
1!
|
||||
b00000000000000000000000000000100 t
|
||||
b1 n0
|
||||
Loading…
Reference in New Issue
Block a user