Start preparing assertions for sorting network
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@ -1,5 +1,6 @@
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from nmigen import *
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from nmigen.utils import *
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from nmigen.asserts import *
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from rtio.sed import layouts
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@ -44,13 +45,23 @@ def cmp_wrap(a, b):
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return Mux((a[-2] == a[-1]) & (b[-2] == b[-1]) & (a[-1] != b[-1]), a[-1], a < b)
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class OutputNetwork(Elaboratable):
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def __init__(self, lane_count, seqn_width, layout_payload):
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def __init__(self, lane_count, seqn_width, layout_payload, *, fv_mode=False):
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m = Module()
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self.m = m
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self.input = [Record(layouts.output_network_node(seqn_width, layout_payload))
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for _ in range(lane_count)]
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self.output = None
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if fv_mode:
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# Model arbitrary inputs for network nodes
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for i in range(lane_count):
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m.d.comb += self.input[i].valid.eq(AnySeq(1))
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m.d.comb += self.input[i].seqn.eq(AnySeq(seqn_width))
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m.d.comb += self.input[i].replace_occured.eq(AnySeq(1))
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m.d.comb += self.input[i].nondata_replace_occured.eq(AnySeq(1))
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for field, width in layout_payload:
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m.d.comb += getattr(self.input[i].payload, field).eq(AnySeq(width))
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step_input = self.input
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for step in boms_steps_pairs(lane_count):
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step_output = []
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@ -98,5 +109,22 @@ class OutputNetwork(Elaboratable):
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self.output = step_output
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step_input = step_output
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if fv_mode:
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# Sanity checks
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assert self.output is not None
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assert len(self.input) == lane_count
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assert len(self.output) == lane_count
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# Indicator of when Past() is valid
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f_past_valid = Signal()
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m.d.sync += f_past_valid.eq(1)
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# TODO: assert outputs is a permutation of inputs
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# Channel numbers for outputs are sorted in increasing order
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with m.If(f_past_valid):
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# TODO: Get the below (bogus) assertion to fail
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m.d.comb += Assert(self.output[7].payload.channel == 0)
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def elaborate(self, platform):
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return self.m
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0
rtio/test/__init__.py
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rtio/test/__init__.py
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rtio/test/sed/__init__.py
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rtio/test/sed/__init__.py
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18
rtio/test/sed/output_network.py
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rtio/test/sed/output_network.py
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@ -0,0 +1,18 @@
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from nmigen import *
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from nmigen.asserts import *
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from nmigen.test.utils import *
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from ...sed.output_network import *
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"""
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Verification tasks for OutputNetwork
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"""
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class OutputNetworkTestCase(FHDLTestCase):
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def verify(self):
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# Bounded model check
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self.assertFormal(
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OutputNetwork(16, 2, [("data", 32), ("channel", 3)], fv_mode=True),
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mode="bmc", depth=10)
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# TODO: unbounded proof
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OutputNetworkTestCase().verify()
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