|
|
4d313ed54a
|
Add SLT instruction
|
2020-08-04 12:34:06 +08:00 |
|
|
|
a6a09ac120
|
Add SLL instruction
|
2020-08-04 12:31:36 +08:00 |
|
|
|
67c57c4d7d
|
Add SUB instruction
|
2020-08-04 12:25:12 +08:00 |
|
|
|
aad9a3f2b5
|
Add ADD instruction
|
2020-08-04 12:20:52 +08:00 |
|
|
|
3abdcf07d2
|
Add R-type instruction format
|
2020-08-04 12:06:01 +08:00 |
|
|
|
19099edee3
|
Add SRAI instruction
|
2020-08-03 15:10:58 +08:00 |
|
|
|
eaf475ee04
|
Add SRLI instruction
|
2020-08-03 14:54:02 +08:00 |
|
|
|
0234b65890
|
Add SLLI instruction
|
2020-08-03 14:51:36 +08:00 |
|
|
|
a9cff77a82
|
Add I-type (shift variation) instruction format
|
2020-08-03 14:44:33 +08:00 |
|
|
|
c3821bc885
|
Add SW instruction
|
2020-08-03 14:29:52 +08:00 |
|
|
|
948a3db1c1
|
Add SH instruction
|
2020-08-03 14:27:08 +08:00 |
|
|
|
84454e7048
|
Add SB instruction
|
2020-08-03 14:23:40 +08:00 |
|
|
|
eebb39ee27
|
Add S-type instruction format
|
2020-08-03 14:15:09 +08:00 |
|
|
|
62ae797737
|
Add BGEU instruction
|
2020-08-03 11:33:57 +08:00 |
|
|
|
596d7fcf6d
|
Add BLTU instruction
|
2020-08-03 11:30:16 +08:00 |
|
|
|
f6008f3096
|
Add BGE instruction
|
2020-08-03 10:42:27 +08:00 |
|
|
|
8d1b070a02
|
Add BLT instruction
|
2020-08-03 10:38:54 +08:00 |
|
|
|
680042b9ee
|
ADD BNE instruction
|
2020-08-03 10:33:45 +08:00 |
|
|
|
486c77a108
|
Fix BEQ instruction
|
2020-08-03 10:29:17 +08:00 |
|
|
|
c17ccdf897
|
Add BEQ instruction
|
2020-08-03 10:28:01 +08:00 |
|
|
|
33ecb317b2
|
Add SB-type instruction
|
2020-08-03 10:19:01 +08:00 |
|
|
|
663b0b3b48
|
Add ANDI instruction
|
2020-07-31 16:51:59 +08:00 |
|
|
|
912580dda8
|
Add ORI instruction
|
2020-07-31 16:49:59 +08:00 |
|
|
|
bf80a13d55
|
Add XORI instruction
|
2020-07-31 16:48:00 +08:00 |
|
|
|
e49476746e
|
Add SLTIU instruction
|
2020-07-31 16:45:15 +08:00 |
|
|
|
305d2195be
|
Add SLTI instruction
|
2020-07-31 16:42:29 +08:00 |
|
|
|
a9bc0629bd
|
Add ADDI instruction
|
2020-07-31 16:39:32 +08:00 |
|
|
|
cf8033a8bb
|
Add LHU instruction
|
2020-07-31 16:35:06 +08:00 |
|
|
|
e3f0727e9c
|
Add LBU instruction
|
2020-07-31 16:31:25 +08:00 |
|
|
|
dc31087f73
|
Add LW instruction
|
2020-07-31 16:27:36 +08:00 |
|
|
|
96015ee5d9
|
Add LH instruction
|
2020-07-31 16:19:04 +08:00 |
|
|
|
ecfe8b11c4
|
Fix JALR instruction
|
2020-07-31 16:15:17 +08:00 |
|
|
|
d525a89ccb
|
Add LB instruction
|
2020-07-31 16:14:48 +08:00 |
|
|
|
ecba1dc3e7
|
Add JALR instruction
|
2020-07-31 16:07:15 +08:00 |
|
|
|
08150e1ecd
|
Add I-type instruction class
|
2020-07-31 14:26:27 +08:00 |
|
|
|
67cba5bf12
|
Add JAL instruction
|
2020-07-31 14:06:55 +08:00 |
|
|
|
b6a68b5b15
|
Add UJ-type instruction class
|
2020-07-31 13:57:52 +08:00 |
|
|
|
7ddfa890dc
|
Add AUIPC instruction
|
2020-07-31 13:44:22 +08:00 |
|
|
|
05266b8474
|
Add LUI instruction
|
2020-07-31 13:40:40 +08:00 |
|
|
|
9cbed8f147
|
Add U-type instruction class
|
2020-07-31 13:29:48 +08:00 |
|
|
|
5274e5b1f1
|
Add generic instruction class
|
2020-07-31 13:06:03 +08:00 |
|
|
|
29c5e52574
|
Categorize RV32IM instructions by type
|
2020-07-31 11:56:22 +08:00 |
|
|
|
aa9967e83d
|
Start over in insns/
|
2020-07-31 11:17:58 +08:00 |
|
|
|
e3273c7e51
|
Fix BGEU instruction
|
2020-07-30 17:37:13 +08:00 |
|
|
|
83e7ab1f05
|
Fix BLTU instruction
|
2020-07-30 16:33:49 +08:00 |
|
|
|
b8e8d10648
|
Fix BGE instruction
|
2020-07-30 16:31:23 +08:00 |
|
|
|
d0de67d09c
|
Fix BLT instruction
|
2020-07-30 16:28:52 +08:00 |
|
|
|
65e4b68517
|
Fix BNE instruction
|
2020-07-30 16:26:29 +08:00 |
|
|
|
4146a2ed20
|
Fix BEQ instruction
|
2020-07-30 16:24:04 +08:00 |
|
|
|
9ddc5563f7
|
Fix JALR instruction
|
2020-07-30 16:19:01 +08:00 |
|
|
|
b583ab728f
|
Fix JAL instruction
|
2020-07-30 16:16:06 +08:00 |
|
|
|
6cff1038be
|
Fix AUIPC instruction
|
2020-07-30 16:12:10 +08:00 |
|
|
|
4d62caadc7
|
Fix U-type instruction format
|
2020-07-30 16:08:24 +08:00 |
|
|
|
e24ddd4269
|
Fix LUI instruction
|
2020-07-30 16:07:47 +08:00 |
|
|
|
9974db7e7b
|
Refactor BGEU instruction
|
2020-07-30 15:53:39 +08:00 |
|
|
|
331cfda279
|
Refactor BLTU instruction
|
2020-07-30 15:49:56 +08:00 |
|
|
|
847099e4de
|
Refactor BGE instruction
|
2020-07-30 15:46:18 +08:00 |
|
|
|
583d165ec1
|
Refactor BLT instruction
|
2020-07-30 15:42:10 +08:00 |
|
|
|
31f6847640
|
Refactor BNE instruction
|
2020-07-30 14:14:24 +08:00 |
|
|
|
3d1bb14bae
|
Refactor BEQ instruction
|
2020-07-30 14:10:48 +08:00 |
|
|
|
4a695c950d
|
Add SB-type instruction format
|
2020-07-30 14:03:59 +08:00 |
|
|
|
f4f5e94843
|
Refactor JALR instruction
|
2020-07-30 13:56:30 +08:00 |
|
|
|
e6c6f0462e
|
Add I-type instruction format
|
2020-07-30 13:48:01 +08:00 |
|
|
|
7846ba95ac
|
Refactor JAL instruction
|
2020-07-30 13:34:52 +08:00 |
|
|
|
a84b6d50b8
|
Add UJ-type instruction format
|
2020-07-30 13:15:17 +08:00 |
|
|
|
3dc2a174fd
|
Refactor AUIPC instruction
|
2020-07-30 13:01:13 +08:00 |
|
|
|
927c12e97c
|
Refactor LUI instruction
|
2020-07-30 12:55:57 +08:00 |
|
|
|
34c8b6cf3d
|
Create U-type instruction format
|
2020-07-30 12:45:32 +08:00 |
|
|
|
c9c47ddc35
|
Create general instruction class
|
2020-07-30 12:06:51 +08:00 |
|
|
|
2421f1f6b6
|
Add RV32IM ISA
|
2020-07-24 13:51:04 +08:00 |
|
|
|
5bce84836c
|
Add REMU instruction for RV32M
|
2020-07-24 13:32:43 +08:00 |
|
|
|
4600eaeb74
|
Add REM instruction for RV32M
|
2020-07-24 13:30:06 +08:00 |
|
|
|
7f3f88cb69
|
Add DIVU instruction for RV32M
|
2020-07-24 13:27:48 +08:00 |
|
|
|
2b198303c6
|
Add DIV instruction for RV32M
|
2020-07-24 13:25:17 +08:00 |
|
|
|
f13208455d
|
Add MULHU instruction for RV32M
|
2020-07-24 13:22:41 +08:00 |
|
|
|
7a61919a88
|
Add MULHSU instruction for RV32M
|
2020-07-24 13:20:05 +08:00 |
|
|
|
9b4f6ac359
|
Add MULH instruction for RV32M
|
2020-07-24 13:16:47 +08:00 |
|
|
|
c72205d433
|
Modify MUL instruction to use alternative operations
|
2020-07-24 13:13:03 +08:00 |
|
|
|
dec39cb11d
|
Re-add MUL instruction
|
2020-07-24 12:55:11 +08:00 |
|
|
|
f33d229b2c
|
Fix XOR instruction
|
2020-07-24 12:49:33 +08:00 |
|
|
|
d54269d3f0
|
Fix SUB instruction
|
2020-07-24 12:48:08 +08:00 |
|
|
|
fe2ff5150a
|
Fix SRL instruction
|
2020-07-24 12:46:24 +08:00 |
|
|
|
6d35ecdc80
|
Fix SRA instruction
|
2020-07-24 12:44:44 +08:00 |
|
|
|
3c1510ebbc
|
Fix SLT instruction
|
2020-07-24 12:42:27 +08:00 |
|
|
|
18e43d9689
|
Fix SLL instruction
|
2020-07-24 12:40:28 +08:00 |
|
|
|
d59ebda628
|
Fix OR instruction
|
2020-07-24 12:32:59 +08:00 |
|
|
|
3028246b73
|
Fix AND instruction
|
2020-07-24 12:24:43 +08:00 |
|
|
|
eedfc843f7
|
Fix ADD instruction
|
2020-07-24 12:21:07 +08:00 |
|
|
|
73005eb3c3
|
Revert MUL instruction
|
2020-07-24 12:17:02 +08:00 |
|
|
|
14c87fdde2
|
Add MUL instruction for RV32M
|
2020-07-24 12:13:40 +08:00 |
|
|
|
35a53071aa
|
Complete generator for RV32I ISA
|
2020-07-23 14:33:25 +08:00 |
|
|
|
2e7cc106aa
|
Add missing return in ports in RV32I ISA
|
2020-07-23 12:57:32 +08:00 |
|
|
|
badd480a45
|
Prepare generator script for RV32I ISA
|
2020-07-23 12:42:59 +08:00 |
|
|
|
d54a60879d
|
Add list of supported instructions for RV32I
|
2020-07-23 11:18:41 +08:00 |
|
|
|
61393b9a4f
|
Add AND instruction for RV32I
|
2020-07-22 16:39:08 +08:00 |
|
|
|
93978ccdb4
|
Add OR instruction for RV32I
|
2020-07-22 16:36:40 +08:00 |
|
|
|
4eae7064fb
|
Add SRA instruction for RV32I
|
2020-07-22 16:32:51 +08:00 |
|
|
|
ada2a09818
|
Add SRL instruction for RV32I
|
2020-07-22 16:16:27 +08:00 |
|
|
|
192aec2347
|
Add XOR instruction for RV32I
|
2020-07-22 16:11:58 +08:00 |
|
|
|
c6c18765f5
|
Add SLTU instruction for RV32I
|
2020-07-22 16:08:09 +08:00 |
|
