Add SW instruction

insns/insn_sw.py

@@ -0,0 +1,23 @@
+from insn_S import *
+
+class rvfi_insn_sw(rvfi_insn_S):
+    def __init__(self):
+        super(rvfi_insn_sw, self).__init__()
+    def ports(self):
+        return super(rvfi_insn_sw, self).ports()
+    def elaborate(self, platform):
+        m = super(rvfi_insn_sw, self).elaborate(platform)
+
+        # SW instruction
+        addr = Signal(32)
+        m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0100011))
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
+        m.d.comb += self.spec_mem_addr.eq(addr)
+        m.d.comb += self.spec_mem_wmask.eq((1 << 4) - 1)
+        m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
+        m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
+
+        return m