Fix SLL instruction
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@ -47,7 +47,7 @@ class rvfi_insn_sll(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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# R-type instruction format (shift variation)
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# R-type instruction format
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insn_padding = Signal(self.RISCV_FORMAL_ILEN)
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m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
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insn_funct7 = Signal(7)
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