M-Labs
/
riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Fix U-type instruction format

pull/1/head
Donald Sebastian Leung 2020-07-30 16:08:24 +08:00
parent e24ddd4269
commit 4d62caadc7
1 changed files with 0 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
insns/insn_U_type.py
View File

@ -21,13 +21,4 @@ class rvfi_insn_U_type(rvfi_insn_general):
m.d.comb += self.misa_ok.eq(1)
# default assignments
m.d.comb += self.spec_rs1_addr.eq(0)
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~self.misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m