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7062 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 2f7364563c nix: fix breakage introduced by nixpkgs 6f05dea3 2019-02-04 19:28:36 +08:00
Sebastien Bourdeauducq 5a7460a38e kasli: add sync delays to device_db_berkeley 2019-02-01 22:14:03 +08:00
Sebastien Bourdeauducq ea431b6982 sayma_rtm: use 150MHz RTIO freq for DDMTD 2019-01-31 20:43:44 +08:00
Sebastien Bourdeauducq ec230d6560 sayma: move SYSREF DDMTD to the RTM 
Put RTM Si5324 into bypass mode before running.
Needs rework to cut RTM Si5324 reset trace.
Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315.
Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic).
 2019-01-31 20:39:33 +08:00
Sebastien Bourdeauducq 8119000982 sayma_rtm_drtio: use Si5324 soft reset 
Needs easy board rework to cut trace at pin 1 of Si5324.
The Si5324 contains an internal pull-up on that pin.

Allows using Si5324 + HMC7043 chips at the same time.

Allows the Si5324 bypass hack for DDMTD experiments on the RTM.
 2019-01-31 19:43:54 +08:00
Sebastien Bourdeauducq 82106dcd95 si5324: add bypass function 2019-01-31 19:38:55 +08:00
Sebastien Bourdeauducq 8bbd4207d8 si5324: use consistent bitmask 2019-01-31 19:35:56 +08:00
Sebastien Bourdeauducq bdb6678cec nix: bump migen 2019-01-31 15:13:17 +08:00
Sebastien Bourdeauducq d3c608aaec jesd204sync: reset and check lock status of DDMTD helper PLL in firmware 2019-01-31 15:11:16 +08:00
Sebastien Bourdeauducq fa3b40141d hmc830_7043: document sayma clock muxes 2019-01-31 15:10:11 +08:00
Sebastien Bourdeauducq ec8560911f siphaser: bugfixes 
* Fix integer overflow in degree computation
* Add some phase slips after the first transition to get out of the jitter zone and avoid intermittent short windows
 2019-01-30 16:56:38 +08:00
Sebastien Bourdeauducq c591009220 sayma: report TSC phase of SYSREF (TSC LSBs on SYSREF rising edge) in SYSREF sampler 
Better visibility, better diagnostics, allows some changing of SYSREF frequency while keeping the same gateware.
 2019-01-29 23:30:01 +08:00
Sebastien Bourdeauducq 9d0d02a561 jesd204sync: increase tolerance for coarse->final target in calibrate_sysref_target 
There is plenty of slack (it only needs to meet timing at the RTIO frequency).
 2019-01-29 16:48:55 +08:00
Sebastien Bourdeauducq ed6aa29897 jesd204sync: print more information on test_slip_ddmtd error 2019-01-29 16:47:29 +08:00
Sebastien Bourdeauducq 2e8decbce3 kasli_sawgmaster: generate a HMC830 clock with Urukul 2019-01-29 15:06:45 +08:00
Sebastien Bourdeauducq 9ae57fd51e sayma: pass rtio_clk_freq to DDMTD core 2019-01-29 15:06:45 +08:00
Robert Jördens 90c9fa446f test: add array transfer test 
200 kB/s, more than a factor of 10 slower than the bare string transfer

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-28 14:30:44 +00:00
Sebastien Bourdeauducq 7a5d28b73d jesd204sync: test SYSREF period 2019-01-28 19:11:38 +08:00
Sebastien Bourdeauducq 1a42e23fb4 jesd204sync: print DDMTD SYSREF final alignment delta 2019-01-28 18:39:16 +08:00
Sebastien Bourdeauducq eebff6d77f jesd204sync: fix max_phase_deviation 2019-01-28 18:38:18 +08:00
Sebastien Bourdeauducq b9e3fab49c jesd204sync: improve messaging 2019-01-28 18:37:46 +08:00
Sebastien Bourdeauducq 145f08f3fe jesd204sync: update SYSREF S/H limit deviation tolerance 
Follows the increased DDMTD resolution.
 2019-01-28 18:21:31 +08:00
Sebastien Bourdeauducq ba21dc8498 jesd204sync: improve messaging 2019-01-28 18:08:20 +08:00
Sebastien Bourdeauducq 3acee87df2 firmware: improve DDMTD resolution using dithering/averaging 2019-01-28 16:04:04 +08:00
Sebastien Bourdeauducq cfe66549ff jesd204sync: cleanup DDMTD averaging code 2019-01-28 14:14:50 +08:00
Sebastien Bourdeauducq 2b0d63db23 hmc830_7043: support 125MHz RTIO 2019-01-28 13:44:08 +08:00
Sebastien Bourdeauducq bdd4e52a53 ad9154: support 125MHz RTIO 2019-01-28 13:43:52 +08:00
Sebastien Bourdeauducq 47312e55d3 sayma: set RTIO_FREQUENCY in MasterDAC 2019-01-28 13:43:28 +08:00
Sebastien Bourdeauducq 443d6d8688 sayma_amc: pass RTIO clock frequency to SiPhaser 2019-01-28 09:49:03 +08:00
Sebastien Bourdeauducq 3b6f47886e firmware: print more info on DDMTD stability error 2019-01-27 23:06:11 +08:00
Sebastien Bourdeauducq 74fdd04622 firmware: test DDMTD stability 2019-01-27 20:39:12 +08:00
Sebastien Bourdeauducq 81b0046f98 ddmtd: add deglitchers 2019-01-27 20:38:41 +08:00
Sebastien Bourdeauducq 8254560577 sayma: properly determine SYSREF coarse calibration target 2019-01-27 16:00:36 +08:00
Sebastien Bourdeauducq 214394e3b0 sayma: reimplement DAC SYSREF autocalibration 2019-01-27 15:28:39 +08:00
Sebastien Bourdeauducq fdbf1cc2b2 sayma: rework DAC SYSREF margin validation 
Previous code did not work when delay range was not enough for two rotations.
This removes autocalibration, to be done later. Uses hardcoded value for now.
 2019-01-27 14:17:54 +08:00
Sebastien Bourdeauducq 7e5c062c2c firmware: bypass channel divider for HMC7043 DCLK 2019-01-27 11:49:34 +08:00
Sebastien Bourdeauducq f73ffe44f9 firmware: implement DDMTD-based SYSREF/RTIO alignment (draft) 
Mostly works and usually gets the DAC synchronized at 2.4GHz with Urukul across DRTIO.

Needs cleanup and optimization/characterization.
 2019-01-27 09:51:24 +08:00
Sebastien Bourdeauducq 8632b553d2 ddmtd: use IOB register to sample input 2019-01-27 09:50:02 +08:00
Sebastien Bourdeauducq d1ef036948 kasli_sawgmaster: initialize SAWG phase according to RTIO TSC 2019-01-27 09:49:31 +08:00
Sebastien Bourdeauducq 9966e789fc sayma: simplify Ultrascale LVDS T false path 
Recommended by Xilinx.
 2019-01-25 23:40:48 +08:00
Sebastien Bourdeauducq 359fb1f207 sayma: fix DDMTD STA 2019-01-25 23:39:19 +08:00
Sebastien Bourdeauducq cb04230f86 sayma: SYSREF setup/hold validation demonstration 
This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
 2019-01-25 16:58:58 +08:00
Sebastien Bourdeauducq 3356717316 sayma: DDMTD SYSREF measurement demonstration 2019-01-25 16:00:31 +08:00
Sebastien Bourdeauducq 4941fb3300 sayma: 2.4GHz DAC clocking (4X interpolation) 
* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
 2019-01-25 13:47:04 +08:00
Sebastien Bourdeauducq cc9420d2c8 hmc7043: fix divider programming 2019-01-25 11:48:50 +08:00
Robert Jördens 8c5a502591 ad53xx: ignore F3 (reserved) 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-24 15:50:46 +01:00
Sebastien Bourdeauducq bbac92442f sayma: check hmc7043 slip period 2019-01-24 20:13:43 +08:00
Sebastien Bourdeauducq a92cc91dcb kasli_sawgmaster: correctly tune DDS and SAWG 2019-01-24 19:37:14 +08:00
Sebastien Bourdeauducq f8b39b0b9a sayma: enable 2X DAC interpolation 
Seems to work just fine and gets one clock divider out of the way.
 2019-01-24 18:28:01 +08:00
Sebastien Bourdeauducq 07b5b0d36d kasli: adapt Master target to new hardware 2019-01-24 18:27:15 +08:00