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Commit Graph

6167 Commits

Author SHA1 Message Date
88fb9ce4d6 sayma_rtm: add hmc7043_gpo monitoring 2018-07-11 19:04:29 +08:00
29e5c95afa sayma_rtm: minor cleanup 2018-07-11 19:02:59 +08:00
7f05e0c121 sayma_rtm: remove UART loopback
RTM power supply issues are fixed now, plus this will get in the way of satman support.
2018-07-11 19:00:18 +08:00
f8ceea20d0 grabber: add new ROI engine (untested) 2018-07-10 17:06:17 +08:00
d82beee540 grabber: make parser EOP a pulse 2018-07-10 17:04:07 +08:00
701c93d46c grabber: add false path constraints 2018-07-10 14:28:23 +08:00
6a77032fa5 grabber: use BUFR/BUFIO
Less jitter and frees up BUFGs.
2018-07-10 13:30:38 +08:00
208dc7c218 grabber: prevent glitches in last_x/last_y cdc 2018-07-10 12:56:37 +08:00
c4e3c66265 grabber: add clock constraint 2018-07-10 12:37:32 +08:00
d51294649e conda: bump migen/misoc 2018-07-10 12:26:24 +08:00
David Nadlinger
768b970deb Fixup 4359a437 (tuples of lists), add regression tests 2018-07-10 01:18:51 +01:00
David Nadlinger
edc314524c test_embedding: Remove unused reference to led device 2018-07-10 01:11:47 +01:00
4f56710e4b grabber: add parser, report detected frame size in core device log 2018-07-10 02:06:37 +08:00
37e303dafc gitmodules: remove empty file 2018-07-09 19:32:29 +02:00
2d4af509c2 readthedocs.yml: drop (out of date, not working) 2018-07-09 19:31:27 +02:00
David Nadlinger
4359a43732 compiler: Indirection status of TTuple depends on elements
For instance, TTuple(TList(TInt32())) has indirections, while
TTuple(TInt32()) does not.

This fixes memory corruption with RPCs that return tuples of lists.

Signed-off-by: David Nadlinger <code@klickverbot.at>
2018-07-09 18:49:50 +08:00
d2c8e62cb7 test_rtio: relax ClockGeneratorLoopback performance requirements 2018-07-09 18:07:25 +08:00
423929a125 test: relax min transfer rates from 2MB/s to 1.9MB/s 2018-07-09 18:00:24 +08:00
9153c4d8a3 use tokenize.open() to open Python source files
Fixes encoding issues especially with device databases modified in obscure editors.
2018-07-07 17:04:56 +08:00
4420046502 kasli_tester: support mixed AD9910/AD9912 systems 2018-07-06 15:43:38 +08:00
ac3f360c26 kasli_tester: fix AD9912 support 2018-07-06 15:43:25 +08:00
509562ddbf kasli: add WIPM target 2018-07-06 15:41:28 +08:00
4eb26c0050 hmc7043: enable group 5 2018-07-03 14:16:31 +02:00
16b917be5d doc: add reminder of what positive slack means. Closes #1084 2018-07-02 16:23:12 +08:00
540bdae99c grabber: enable DIFF_TERM on inputs 2018-07-01 09:28:51 +08:00
0483b8d14c sayma_drtio: ditto 2018-06-28 17:03:32 +08:00
04d6ff45c8 kasli_sawgmaster: reset SAWGs
Most importantly this resets the phase accumulators.
2018-06-28 17:01:48 +08:00
729ce58f98 sayma: use GTP_CLK1 to clock DRTIO satellite transceiver
This is required to get constant skew between the DRTIO transceiver clock
(which then generates the RTIO clock) and the siphaser reference clock.

Both the Si5324 and the RTM clock tree have non-deterministic in-to-out skew
at 150MHz due to dividers.
2018-06-28 11:23:40 +08:00
a65721d649 sayma: put RTM clock tree into the siphaser loop
* Fixes one bug where siphaser was one Si5324 output and the rest of the
system was clocked by the other. With the Si5324 settings we have, skew
between the outputs is not controlled.
* Puts the coaxial cable between AMC and RTM into the siphaser loop.
2018-06-27 21:46:55 +08:00
d49716dfac satman: tune Sayma SYSREF phases 2018-06-27 18:09:35 +08:00
46c044099c hmc7043,satman: verify alignment of SYSREF slips 2018-06-27 17:36:13 +08:00
7dfd70c502 hmc7043: make margin_{minus,plus} consistent with ad9154 2018-06-27 17:35:26 +08:00
4bbdd43bdf hmc7043: do not freeze if SYSREF slip fails 2018-06-27 17:32:56 +08:00
a8a2ad68d3 runtime: tune Sayma SYSREF phases 2018-06-27 17:31:29 +08:00
apatura-iris
e9a1e10221 Update installing.rst
Added comment to clarify that ``artiq-main`` is the conda environment.
2018-06-27 08:18:50 +02:00
apatura-iris
5e5cdf0e67 Update installing.rst
The file 99-openocd.rules as downloaded from githubusercontent.com seems to be outdated and does now work on Ubuntu 16.04. The version that ships with OpenOCD has an additional ``TAG+="uaccess"`` in the rules file and works fine. Thus I suggest to use the file that is bundled with OpenOCD.
2018-06-27 08:18:50 +02:00
811882943b artiq_flash: RTM gateware is not required for master variant 2018-06-25 18:28:55 +08:00
c750de2955 sayma: add many-port pure DRTIO master 2018-06-25 18:21:22 +08:00
84b3d9ecc6 bootloader: also check firmware CRC in SDRAM (#1065) 2018-06-23 11:28:12 +08:00
68530fde07 sayma: generate 100MHz from Si5324 on standalone and master targets
* Allow switching between DRTIO satellite and standalone without
  touching the hardware.
* Allow operating standalone and master without an additional RF
  signal generator.
2018-06-23 10:44:38 +08:00
whitequark
b6dd9c8bb0 runtime: support builds without RTIO DMA.
Fixes #1079.
2018-06-23 00:56:21 +00:00
whitequark
12fde6d34b artiq_coremgmt: fix typo.
Fixes #1056.
2018-06-23 00:36:59 +00:00
51a5d8dff9 examples: add Kasli SAWG master 2018-06-22 18:57:49 +08:00
f87da95e57 jesd204: use jesd clock domain for sysref sampler
RTIO domain is still in reset during calibration.
2018-06-22 17:13:01 +08:00
76fc63bbf7 jesd204: use separate controls for reset and input buffer disable 2018-06-22 11:38:18 +08:00
d9955fee76 jesd204: make sure IOB FF is used to sample SYSREF at FPGA 2018-06-22 11:00:56 +08:00
60b22217ce sayma: set DRTIO master HMC830_REF to 100MHz 2018-06-22 10:10:09 +08:00
e6d1726754 sayma: add RTIO log to DRTIO master 2018-06-22 00:05:22 +08:00
83428961ad sayma: add SAWG and JESD to DRTIO master 2018-06-22 00:04:22 +08:00
c1db02a351 drtio/gth_ultrascale: disable IBUFDS_GTE3 until stable_clkin
Precaution against HMC7043 noise issues.
2018-06-21 22:56:07 +08:00