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Commit Graph

6227 Commits

Author SHA1 Message Date
66dee9d1ad drtio: send/process I2C and SPI aux packets (#740) 2017-06-21 16:50:51 +08:00
f58f16ccd4 drtioaux: add default timeout 2017-06-21 16:23:11 +08:00
7675dd063b drtioaux: add I2C and SPI packets (#740) 2017-06-21 14:07:16 +08:00
c399bec8da RELEASE_NOTES: pipistrello discontinued by manufacturer 2017-06-20 06:18:34 +02:00
c74de6ae96 phaser: reintroduce test_ad9154_status 2017-06-20 00:49:57 +08:00
8c56a95fa2 spi: add default busno 2017-06-20 00:49:38 +08:00
39ddb66f0f phaser: add AD9154 SPI access driver to example ddb 2017-06-20 00:49:21 +08:00
470bce6214 coredevice: add AD9154 SPI access driver 2017-06-20 00:48:50 +08:00
a6d06824e7 fix indentation 2017-06-20 00:12:11 +08:00
8f2d85fc5b add back ad9154_reg.py 2017-06-19 23:45:32 +08:00
c86029bca2 i2c: expose restart as syscall, add structure for I2C-over-DRTIO 2017-06-19 23:44:51 +08:00
268b7d8aaf typo 2017-06-19 15:42:10 +08:00
09d198c7a1 test: add test for exception on non-existent I2C bus 2017-06-19 15:32:09 +08:00
d08bd58dff versioneer: cut git hashes consistently (#753) 2017-06-19 15:31:48 +08:00
6c6bb67618 libboard: fix compiler warning on not(has_i2c) 2017-06-19 14:57:15 +08:00
5d63489080 i2c,spi: add busno error detection 2017-06-19 14:27:30 +08:00
0d8067256b rtio: refactor RelaxedAsyncResetSynchronizer 2017-06-18 14:37:08 +02:00
8399f8893d add kernel access to non-realtime SPI buses (#740) 2017-06-18 12:45:07 +08:00
424b2bfbd8 rtio: describe rio and rio_phy domains a bit more 2017-06-17 12:21:07 +02:00
219dfd8984 rtio: add one register level for rio and rio_phy resets
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
2017-06-17 12:17:48 +02:00
8fea361412 firmware: always use 8 characters to abbreviate git commit hashes 2017-06-17 14:43:50 +08:00
e19bfd4781 test_sawg_fe: add ref_multiplier to simulated core 2017-06-16 19:45:24 +02:00
b5772f478a sawg: add channel reset (closes #751) 2017-06-16 19:31:57 +02:00
2a76034fbc cri: add note about clearing of o_data 2017-06-16 19:06:00 +02:00
10fb6c6216 conda: set ignore_prefix_files on all board packages 2017-06-15 16:25:52 +08:00
5e94810e84 Revert "Revert "conda: use new noarch system for board packages as well""
This reverts commit 832fb139a0.
2017-06-15 16:10:58 +08:00
832fb139a0 Revert "conda: use new noarch system for board packages as well"
Never missing an opportunity to be awful, conda helps itself with the .fbi files and merrily patches the strings inside them that contain paths resembling the conda build folder, resulting of course in corrupption and CRC errors.

This reverts commit c856b22579.
2017-06-15 16:00:00 +08:00
fecc42fd0c sawg/phaser: expand documentation (closes #750) 2017-06-14 11:49:52 +02:00
ed2b27fed2 conda: fix pythonparser dependency 2017-06-14 12:39:29 +08:00
whitequark
53f7d145a4 conda: update pythonparser dependency. 2017-06-14 03:35:54 +00:00
858c1be381 sawg: expand documentation 2017-06-13 18:51:48 +02:00
3f37870e25 sawg: register pre-hbf adder 2017-06-13 18:15:44 +02:00
e229edd5d5 sawg: add register after hbf for timing 2017-06-12 23:08:27 +02:00
315338fca9 test/sawg: test HBF overshoot, fix sim patching 2017-06-12 20:35:47 +02:00
9a8a7b9102 sawg: handle clipping interpolator
* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC

This leaves a factor of two headroom for the sum of the following
effects:

  * HBF overshoot (~15 % of the step)
  * A1/A2 DDS sum

While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?

closes #743
2017-06-12 20:33:54 +02:00
1fb3995ffc Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)"
This reverts commit 6ac9d0c41e.

Overshooting behavior must to be handled outside the FIR.
2017-06-12 20:07:25 +02:00
332bcc7f3b fir: check widths 2017-06-12 20:07:23 +02:00
39a1dcbb3d test/fir: look at overshoot behavior 2017-06-12 20:06:07 +02:00
6ac9d0c41e fir/ParallelHBFUpsampler: add headroom (gain=2)
This addresses part of #743
2017-06-12 18:59:45 +02:00
566ff73dff pdq: unify spi-PDQ and usb-PDQ protocols 2017-06-10 15:03:25 +02:00
6c54c0f834 sawg: update example 2017-06-10 11:52:48 +02:00
d8aee931ba sawg: extend phase mode docs 2017-06-09 12:26:49 +02:00
whitequark
f7254dd3ce compiler.validators.constness: take AugAssign into account. 2017-06-09 07:31:08 +00:00
whitequark
ad2ee714c2 compiler: do not permit iterating str values.
This currently breaks badly on UTF-8, and doesn't even return
a value of a correct type.
2017-06-09 07:29:31 +00:00
whitequark
4e7493843a compiler: Constness is a validator, not analysis. 2017-06-09 07:29:31 +00:00
whitequark
5d841d08e9 compiler: do not permit mutation of bytes values (#714). 2017-06-09 07:29:28 +00:00
whitequark
284382b1f5 compiler: add support for bytearray values in RPC (#714). 2017-06-09 07:15:25 +00:00
whitequark
9ed4e9c1cd compiler: add support for printing of bytearray values (#714). 2017-06-09 07:15:25 +00:00
whitequark
e9564b15c8 compiler: add support for bytearray type (#714). 2017-06-09 07:15:24 +00:00
whitequark
5b4fde30a8 compiler: unbreak subscripts for bytes values (#714). 2017-06-09 07:10:48 +00:00