M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity
6,675 Commits 13 Branches 35 Tags 26 MiB
Commit Graph

6675 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq cf9447ab77 rtio/cri: remove unneeded CSR management 2019-01-05 23:40:45 +08:00
Sebastien Bourdeauducq 2c3510497b firmware: fix not(has_spiflash) build 2019-01-05 23:40:03 +08:00
Sebastien Bourdeauducq d6fea22174 manual: update firmware/gateware build/flashing instructions. Closes #1223 2019-01-05 12:38:54 +08:00
Sebastien Bourdeauducq 2100a8b1f1 sayma_amc: more fighting with vivado timing analyzer 2019-01-05 12:25:30 +08:00
Drew 94cdad6c1d artiq_flash: change docs from old `-m` arg to `-V` (#1224) (#1227) 
`-m` argument is deprecated. Changed to newer `-V` argument
Closes #1224

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
 2019-01-05 10:22:12 +08:00
Drew Risinger b58d59a9e7 pyon: fix grammar in module docstring. 
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
 2019-01-04 19:31:08 +00:00
Drew 3e5cea5d89 Docs: instructions to check if in plugdev group 2019-01-04 19:30:13 +00:00
Sebastien Bourdeauducq a93fdb8c9d drtio: disable all destinations in gateware at startup 
Otherwise, kernels fail to get a RTIODestinationUnreachable exception when attempting
to reach a DRTIO destination that has never been up.
 2019-01-04 23:42:12 +08:00
Sebastien Bourdeauducq 62d7c89c48 sayma_amc: use high-resolution TTL on SMAs (#792) 2019-01-03 20:50:38 +08:00
Sebastien Bourdeauducq 0972d61e81 ttl_serdes_ultrascale: use GTH clock domains 2019-01-03 20:50:04 +08:00
Sebastien Bourdeauducq f007895fad drtio/gth_ultrascale: fix rtiox clock domain 2019-01-03 20:49:38 +08:00
Sebastien Bourdeauducq 10ebf63c47 jesd204_tools: get the Vivado timing analyzer to behave 2019-01-03 20:22:35 +08:00
Sebastien Bourdeauducq d6a3172a3e update copyright year 2019-01-03 20:21:34 +08:00
Sebastien Bourdeauducq 4af8fd6a0d ttl_serdes_ultrascale: fix Input 2019-01-03 20:14:54 +08:00
Sebastien Bourdeauducq 175f8b8ccc drtio/gth_ultrascale: generate multiplied RTIO clock from BUFG_GT (#792) 2019-01-03 20:14:18 +08:00
Sebastien Bourdeauducq 77126ce5b3 kasli: use hwrev 1.1 by default for DRTIO examples 2019-01-02 23:04:20 +08:00
Sebastien Bourdeauducq ab9ca0ee0a kasli: use 150MHz for DRTIO by default (Sayma compatibility) 2019-01-02 23:03:57 +08:00
Sebastien Bourdeauducq cc58318500 siphaser: autocalibrate skew using RX synchronizer 
* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
 2019-01-02 22:29:27 +08:00
Sebastien Bourdeauducq f5cda3689e sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant 2019-01-02 16:46:16 +08:00
Sebastien Bourdeauducq e85df13127 nix: update docs 2019-01-02 16:34:29 +08:00
Sebastien Bourdeauducq ec52a1003d nix: add jesd204b 2019-01-02 16:34:11 +08:00
Sebastien Bourdeauducq d42d607547 nix: add microscope 2019-01-02 16:13:08 +08:00
Sebastien Bourdeauducq 7a6bdcb041 nix: fix m-labs URLs 2019-01-02 16:04:25 +08:00
Sebastien Bourdeauducq 48793b7ecf nix: reorganize .nix files 2019-01-01 23:39:38 +08:00
Sebastien Bourdeauducq e2799803cb nix: do not install development packages in user environment 2019-01-01 23:35:55 +08:00
Sebastien Bourdeauducq 1e7ba3227f nix: add development environment 2019-01-01 22:26:32 +08:00
Sebastien Bourdeauducq 421ad9c916 nix: bump llvmlite 2018-12-22 14:01:52 +08:00
Sebastien Bourdeauducq e80d80f133 manual: move to correct directory for building rust crates. Closes #1222 2018-12-21 10:37:08 +08:00
Drew d60b95f481 tdr.py: typo (#1220) 2018-12-18 18:47:09 +00:00
Robert Jördens a7d4d3bda9 ad9910: CONT_RECIRCULATE -> CONT_RAMPUP 2018-12-17 13:25:00 +00:00
Sebastien Bourdeauducq 35bdf26f01 Merge branch 'ad9910-ram' 2018-12-17 21:16:44 +08:00
David Nadlinger e608d6ffd3 coredevice, firmware: Add rtio_input_timestamped_data 
Integration tests to follow as part of an RTIO counter phy that
makes use of this.
 2018-12-15 00:35:04 +00:00
David Nadlinger 8e30c4574b firmware: Treat timestamps consistently as signed [nfc] 
This matches other functions and the ARTIQ Python side, but
isn't actually an ABI change.
 2018-12-15 00:02:18 +00:00
Sebastien Bourdeauducq 38ce7ab8ff sync_struct: handle TimeoutError as subscriber disconnection. Closes #1215 2018-12-13 06:58:54 +08:00
Sebastien Bourdeauducq c09ab8502c nix: cleanup 2018-12-13 06:57:10 +08:00
Joachim Schiele 73941d4661 nix: add rustc, migen and misoc 
This allows firmware compilation.
 2018-12-12 22:24:55 +00:00
Robert Jördens 79eadb9465 ad9910: add RAM mode methods 
* also refactor the CFR1 access into a method

c.f. #1154

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-11 14:54:16 +00:00
Robert Jördens 6df4ae934f eem: name the servo submodule 
This allows the migen namer to derive names for the ADC return clock
domain in the case of multiple SUServos

close #1201

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-11 11:36:40 +01:00
Robert Jördens efd400b02c ad9910: style [nfc] 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-11 11:36:25 +01:00
David Nadlinger d4c393b2a8 firmware/ksupport: Update `cfg(not(has_rtio))` stub signatures 
This fixes up 8caea0e6d3,
but it is unclear whether anyone even uses a `not(has_rtio)`
configuration at this point.
 2018-12-11 01:22:48 +00:00
Robert Jördens d90eb3ae88 ad9910: add read64() 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-07 21:27:00 +00:00
Robert Jördens baf88050fd urukul: expand attenuator HITL unittests 
* read back with cleared backing state
* individual channel settings
* check backing state

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-07 21:06:12 +00:00
Kaifeng cc143d5fec kasli_tester: add support for windows platform. (#1204) 2018-12-05 14:06:45 +01:00
Sebastien Bourdeauducq 6aa341bc44 test_loopback_gate_timing: fix lat_offset 2018-12-02 20:52:32 +08:00
Sebastien Bourdeauducq 421834fa3e compiler: document Target.little_endian 2018-12-02 19:07:18 +08:00
Sebastien Bourdeauducq 981a77834a compiler: use default triple to determine data_layout for JIT 2018-12-02 18:52:13 +08:00
Sebastien Bourdeauducq d931967e5c fix previous commits 2018-12-02 18:32:03 +08:00
Sebastien Bourdeauducq dd03fdfd1a typo 2018-12-02 18:26:54 +08:00
Sebastien Bourdeauducq 8940009e1a compiler: pass data_layout string to llvm.create_target_data before determining endianness 2018-12-02 18:26:19 +08:00
Sebastien Bourdeauducq 2e66788c6c compiler: support little endian target when storing now 2018-12-02 17:40:34 +08:00