2
0
mirror of https://github.com/m-labs/artiq.git synced 2025-01-23 00:56:42 +08:00
Commit Graph

869 Commits

Author SHA1 Message Date
50a62b3d42 liballoc: change align to 16 bytes 2021-09-10 13:25:12 +08:00
7f0bc9f7f0 runtime/makefile: specify emulation, flip endianness 2021-09-10 13:25:12 +08:00
c42adfe6fd runtime.ld: merge .sbss & .bss 2021-09-10 13:25:12 +08:00
f56152e72f rust: fix dependencies 2021-09-10 13:25:12 +08:00
c800b6c8d3 runtime: update rust alloc, managed 2021-09-10 13:25:09 +08:00
e99061b013 runtime: add riscv 2021-09-10 13:23:22 +08:00
ecedec577c runtime: impl riscv exception handling 2021-09-10 13:23:15 +08:00
252594a606 runtime: impl riscv panic handler 2021-09-10 13:20:31 +08:00
31bf17563c personality: update from rust/panic_unwind 2021-09-10 13:20:31 +08:00
bfddd8a30f libdyld: add riscv support 2021-09-10 13:20:31 +08:00
ad3037d0f6 libc: add minimal C types 2021-09-10 13:20:31 +08:00
daaf6c3401 libunwind: add rust interface 2021-09-10 13:20:31 +08:00
6d9cebfd42 satman: handle .sbss generation 2021-09-10 13:20:31 +08:00
96438c9da7 satman: make fbi big-endian 2021-09-10 13:20:31 +08:00
6535b2f089 satman: fix feature 2021-09-10 13:20:31 +08:00
45adaa1d98 satman: add riscv exception handling 2021-09-10 13:20:31 +08:00
869a282410 satman: use riscv 2021-09-10 13:20:31 +08:00
ebb9f298b5 proto_artiq: update alloc type path 2021-09-10 13:20:31 +08:00
97a0132f15 libio: update alloc type path 2021-09-10 13:20:31 +08:00
37ea863004 libio: pin failure version 2021-09-10 13:20:31 +08:00
3ff74e0693 bootloader: handle .sbss generation in .ld
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
448fe0e8cf bootloader: fix panic
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
8294d7fea5 bootloader: swap endianness
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
13032272fd bootloader: add rv32 exception handler
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
46102ee737 board_misoc: build vectors.S with rv64 target in misoc
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
b87ea79d51 rv32: rm irq & vexriscv-rust
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
9aee42f0f2 rv32/boot: remove hotswap
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
82b4052cd6 libboard_misoc: vexriscv integration
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
420891ba54 syntax 2021-08-12 13:01:35 +08:00
9f94bc61ae missing part of 477b1516d 2021-08-12 12:55:37 +08:00
477b1516d3 remove profiler 2021-08-12 12:51:55 +08:00
5111132ef0
ICAP: prevent sayma from using it (#1740) 2021-08-06 15:08:30 +08:00
6b88ea563d
talk to ICAP primitive to restart gateware (#1733) 2021-08-05 17:00:31 +08:00
ea0c7b6173 Merge remote-tracking branch 'harrydrtio/k7-drtio' 2021-06-15 10:04:45 +08:00
92fd705990 increase memory allocated to comms CPU
See discussion in #1612.
2021-02-21 19:06:12 +08:00
14d464b4cf update copyright year 2021-02-17 15:52:08 +08:00
8148fdb8a7
use device endian for core device protocols (#1591) 2021-01-22 16:33:21 +08:00
3832b261b1 firmware: optimize integer array/list rpc 2021-01-21 09:05:17 +01:00
f6d39fd6ba kc705: revive DRTIO master with updated syntax
* KC705 master variant now uses Si5324 as synthesiser.
* Multi-channel has not been implemented yet.
2021-01-20 15:05:31 +08:00
43be383c86 kasli v2.0: drive TX_DISABLE low on all SFPs (fixes #1570)
This was the same problem as #1508 but on SFP1..3
2020-12-23 00:10:12 +08:00
73271600a1 jdcg: STPL tests now perform after DAC initialization 2020-12-14 18:03:31 +08:00
David Nadlinger
d95e619567 compiler: Implement binary NumPy math functions (arctan2, …)
The bulk of the diff is just factoring out the implementation
for binary arithmetic implementations, to be reused for binary
function calls.
2020-11-11 01:35:28 +01:00
David Nadlinger
bc6fbecbda compiler, firmware: Do not expose abort() to kernels
This was only exposed for the assert implementation, and
does not exist on Zynq.
2020-11-10 20:40:18 +01:00
ea95d91428 wrpll: separate collector reset 2020-11-09 17:57:13 +08:00
90017da484 firmware: remove obsolete watchdog code (#1458) 2020-10-15 18:38:00 +08:00
57ee57e7ea runtime: fix metlino si5324 init (2) 2020-10-14 18:41:56 +08:00
ac35548d0f runtime: fix metlino si5324 init 2020-10-14 12:57:25 +08:00
35c61ce24d si5324: unify N31 settings when used as synthesizer
Closes #1528
2020-10-12 14:45:52 +08:00
hartytp
e6ff2ddc32 wrpll: add more diagnostics in firmware and adapt to recent gateware changes 2020-10-08 15:32:27 +08:00
9214e0f3e2 firmware: fix Si5324 CKIN selection on Kasli 2.0
https://github.com/sinara-hw/Kasli/issues/82#issuecomment-702129805
2020-10-02 20:35:32 +08:00