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artiq
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jdcg: STPL tests now perform after DAC initialization

pull/1563/head
Harry Ho 2020-12-10 16:30:28 +08:00 committed by Sebastien Bourdeauducq
parent 3f631c417d
commit 73271600a1
2 changed files with 17 additions and 5 deletions
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21
artiq/firmware/satman/jdcg.rs
View File

@ -108,10 +108,6 @@ pub mod jdac {
basic_request(dacno, jdac_common::PRBS, 0)?;
jesd::prbs(dacno, false);
jesd::stpl(dacno, true);
basic_request(dacno, jdac_common::STPL, 0)?;
jesd::stpl(dacno, false);
basic_request(dacno, jdac_common::INIT, 0)?;
clock::spin_us(5000);
@ -120,7 +116,22 @@ pub mod jdac {
return Err("JESD core reported bad SYNC");
}
info!(" ...done");
info!(" ...done initializing");
}
Ok(())
}
pub fn stpl() -> Result<(), &'static str> {
for dacno in 0..csr::JDCG.len() {
let dacno = dacno as u8;
info!("Running STPL test on DAC-{}...", dacno);
jesd::stpl(dacno, true);
basic_request(dacno, jdac_common::STPL, 0)?;
jesd::stpl(dacno, false);
info!(" ...done STPL test");
}
Ok(())
}

1
artiq/firmware/satman/main.rs
View File

@ -609,6 +609,7 @@ pub extern fn main() -> i32 {
jdcg::jesd::reset(false);
let _ = jdcg::jdac::init();
jdcg::jesd204sync::sysref_auto_align();
jdcg::jdac::stpl();
unsafe {
csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); // unhide
}