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Commit Graph

7354 Commits

Author SHA1 Message Date
d152506ecb sayma: update fmcdio_vhdci_eem demo 2018-07-19 15:47:20 +08:00
8dfcd463aa fmcdio_vhdci_eem: naming consistency 2018-07-19 15:46:04 +08:00
fe93a454d6 fmcdio_vhdci_eem: fix direction shift register permutation and polarity 2018-07-19 15:16:21 +08:00
e71cbe53a6 firmware: cleanup Cargo.lock 2018-07-18 10:37:43 +08:00
31f4f8792a sayma: add Urukul and Zotino to example device_db 2018-07-18 10:31:55 +08:00
25170a53e5 sayma: add back Urukul and Zotino 2018-07-18 10:27:54 +08:00
5e62910a8d examples: add Sayma VHDCI DIO 2018-07-17 23:28:05 +08:00
8b9a8be12a fmcdio_vhdci_eem: add dirctl word computation functions 2018-07-17 23:27:29 +08:00
82145b1263 examples: sayma_drtio → sayma_masterdac 2018-07-17 20:32:30 +08:00
c7d96c2223 conda: bump migen 2018-07-17 20:30:23 +08:00
7fe76426fe fmcdio_vhdci_eem: commit missing part of previous commit 2018-07-17 20:30:13 +08:00
d4d12e264d fmcdio_vhdci_eem: refactor
This allows access to the pin allocation from kernels, which becomes useful
to configure the direction shift register.
2018-07-17 20:13:59 +08:00
4fdc20bb11 sayma: disable Urukul and Zotino for now
Ultrascale I/Os are being a pain as usual and the SPI core won't compile.
2018-07-17 20:08:21 +08:00
8335085fd6 fmcdio_vhdci_eem: fix cc pins 2018-07-17 19:50:34 +08:00
8f7c0c1646 fmcdio_vhdci_eem: fix iostandard 2018-07-17 19:40:34 +08:00
d724bd980c sayma: add EEMs to Master 2018-07-17 18:58:23 +08:00
a0f2d8c2ea gateware: add FMCDIO/EEM adapter definitions 2018-07-17 18:58:16 +08:00
3645a6424e sayma: fix Master build 2018-07-17 18:56:33 +08:00
9b016dcd6d eem: support specifying I/O standard
Xilinx FPGAs require different LVDS I/O standard names depending on I/O bank voltage.
2018-07-17 18:55:17 +08:00
3168b193e6 kc705: remove Zotino and Urukul
* use Kasli instead for using EEMs
* code required outdated VHDCI adapter 1.0
2018-07-17 17:48:57 +08:00
13984385a8 firmware: version → ident 2018-07-15 17:40:17 +08:00
b2695d03ed sayma: remove with_sawg from Master variant 2018-07-15 17:38:29 +08:00
123e7bc054 pyon: sort string dicts by key when pretty-printing. Closes #1010 2018-07-15 17:38:09 +08:00
b27fa8964b add variant in identifier string
Also add without-sawg suffixes on Sayma.

Closes #1060
Closes #1059
2018-07-15 17:21:17 +08:00
b6c70b3cb0 eem: add Zotino monitoring. Closes #1095 2018-07-15 15:35:04 +08:00
8bcba82b65 grabber: reset *_good signals on end of frame
This reduces the amount of time the ROI engine produces invalid output after
being reconfigured.
2018-07-15 15:34:00 +08:00
ea7f925852 Revert "worker_db: Only warn on repeated archive read if dataset changed"
Breaks numpy arrays.

This reverts commit 141fcaaa8a.
2018-07-13 10:41:06 +08:00
46fb5adac3 grabber: fix frequency counter formula 2018-07-12 20:14:38 +08:00
82def6b535 grabber: add frequency counter
Cameras are a bit obscure about what they output, this can help with troubleshooting.
2018-07-12 17:05:18 +08:00
29c35ee553 hmc7043: fix dumb mistake in previous commit 2018-07-12 13:01:41 +08:00
8802b930de hmc7043: add delay after init
Delay required at step 9 of the "Typical Programming Sequence" (page 24 of the datasheet)
2018-07-12 12:37:12 +08:00
c66f9483f8 hmc7043: wait after changing delays
Allows for the SPI transaction to finish, and for the delay to stabilize.
2018-07-12 12:33:53 +08:00
1c191a62bf sayma: tune SYSREF phases 2018-07-12 12:33:35 +08:00
773240bef4 hmc7043: test GPO before using
Based on code by David.
2018-07-12 11:30:24 +08:00
David Nadligner
141fcaaa8a worker_db: Only warn on repeated archive read if dataset changed
In larger experiments, it is quite natural for the same dataset
to be read from multiple unrelated components. The only situation
where multiple reads from an archived dataset are problematic is
when the valeu actually changes between reads. Hence, this commit
restricts the warning to the latter situation.
2018-07-12 10:15:42 +08:00
4843832329 hmc7043: check phase status on init. Closes #1055
Troubleshooting by David.
2018-07-11 19:45:24 +08:00
9397fa7f5a hmc7043: unstick SYSREF FSM (#1055)
Troubleshooting by David.

Additionally, register 7D is broken.
Checking phase init state has to be done through another means.
2018-07-11 19:11:01 +08:00
88fb9ce4d6 sayma_rtm: add hmc7043_gpo monitoring 2018-07-11 19:04:29 +08:00
29e5c95afa sayma_rtm: minor cleanup 2018-07-11 19:02:59 +08:00
7f05e0c121 sayma_rtm: remove UART loopback
RTM power supply issues are fixed now, plus this will get in the way of satman support.
2018-07-11 19:00:18 +08:00
f8ceea20d0 grabber: add new ROI engine (untested) 2018-07-10 17:06:17 +08:00
d82beee540 grabber: make parser EOP a pulse 2018-07-10 17:04:07 +08:00
701c93d46c grabber: add false path constraints 2018-07-10 14:28:23 +08:00
6a77032fa5 grabber: use BUFR/BUFIO
Less jitter and frees up BUFGs.
2018-07-10 13:30:38 +08:00
208dc7c218 grabber: prevent glitches in last_x/last_y cdc 2018-07-10 12:56:37 +08:00
c4e3c66265 grabber: add clock constraint 2018-07-10 12:37:32 +08:00
d51294649e conda: bump migen/misoc 2018-07-10 12:26:24 +08:00
David Nadlinger
768b970deb Fixup 4359a437 (tuples of lists), add regression tests 2018-07-10 01:18:51 +01:00
David Nadlinger
edc314524c test_embedding: Remove unused reference to led device 2018-07-10 01:11:47 +01:00
4f56710e4b grabber: add parser, report detected frame size in core device log 2018-07-10 02:06:37 +08:00