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hmc7043: check phase status on init. Closes #1055
Troubleshooting by David.
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9397fa7f5a
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@ -197,6 +197,12 @@ pub mod hmc7043 {
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}
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}
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fn spi_wait_idle() {
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unsafe {
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while csr::converter_spi::idle_read() == 0 {}
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}
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}
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fn write(addr: u16, data: u8) {
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let cmd = (0 << 15) | addr;
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let val = ((cmd as u32) << 8) | data as u32;
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@ -259,6 +265,17 @@ pub mod hmc7043 {
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write(0x1, 0x48); // mute all outputs
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}
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/* Read an HMC7043 internal status bit through the GPO interface.
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* This method is required to work around bugs in the register interface.
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*/
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fn gpo_indirect_read(mux_setting: u8) -> bool {
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write(0x50, (mux_setting << 2) | 0x3);
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spi_wait_idle();
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unsafe {
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csr::hmc7043_gpo::in_read() == 1
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}
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}
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pub fn init() {
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spi_setup();
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info!("loading configuration...");
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@ -266,7 +283,6 @@ pub mod hmc7043 {
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write(0x3, 0x14); // Disable the REFSYNCIN reseeder
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write(0xA, 0x06); // Disable the REFSYNCIN input buffer
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write(0xB, 0x07); // Enable the CLKIN input as LVPECL
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write(0x50, 0x1f); // Disable GPO pin
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write(0x9F, 0x4d); // Unexplained high-performance mode
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write(0xA0, 0xdf); // Unexplained high-performance mode
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@ -320,6 +336,19 @@ pub mod hmc7043 {
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info!(" ...done");
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}
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pub fn check_phased() -> Result<(), &'static str> {
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if !gpo_indirect_read(3) {
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return Err("GPO reported phases did not align");
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}
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// Should be the same as the GPO read
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let sysref_fsm_status = read(0x91);
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if sysref_fsm_status != 0x2 {
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error!("Bad SYSREF FSM status: {:02x}", sysref_fsm_status);
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return Err("Bad SYSREF FSM status");
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}
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Ok(())
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}
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pub fn sysref_offset_dac(dacno: u8, phase_offset: u16) {
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/* Analog delay resolution: 25ps
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* Digital delay resolution: 1/2 input clock cycle = 416ps for 1.2GHz
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@ -434,6 +463,7 @@ pub fn init() -> Result<(), &'static str> {
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hmc7043::enable();
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hmc7043::detect()?;
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hmc7043::init();
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hmc7043::check_phased()?;
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Ok(())
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}
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