17 Commits

Author	SHA1	Message	Date
mwojcik	db1c9d336e	aux_controller: fix class parent	2021-10-04 08:53:38 +02:00
mwojcik	38088cea87	cleanup, less unnecessary comments and dup code	2021-10-01 15:35:00 +02:00
mwojcik	f23c6cdb18	aux_controller: fix axi sram data paths	2021-09-29 14:01:06 +02:00
mwojcik	8ab2b3f299	aux_controller: connect r/w/b lanes to axi bus	2021-09-29 11:50:52 +02:00
mwojcik	9c09216281	updated gateware for not yet published migen-axi changes	2021-09-13 15:06:34 +02:00
mwojcik	d3152f3d24	changed auxctrl tx/rx memory to axi2csr_sram	2021-09-10 15:25:05 +02:00
mwojcik	b2d9003d9f	drtioaucontroller: made two decoders	2021-08-20 15:13:56 +02:00
mwojcik	e43684a3ed	moved AXI SRAM to migen-axi	2021-08-18 12:36:17 +02:00
mwojcik	7b868e1c9d	few fixes, typos and missed unnecessary statements	2021-08-17 13:16:02 +02:00
mwojcik	61f81cec47	sram: redesigned write FSM. removed unused signals	2021-08-17 11:10:08 +02:00
mwojcik	3e1d14ff38	replaced increment logic with ready Incr module	2021-08-16 15:33:50 +02:00
mwojcik	67ed7fae78	sram: or operator in wrong place for wrapped burst	2021-08-16 12:05:23 +02:00
mwojcik	f015d6732b	sram: support for different burst settings on read	2021-08-16 11:51:50 +02:00
mwojcik	b6dd5bea68	sram: fixed wrong assumptions on some signals	2021-08-13 14:58:18 +02:00
mwojcik	bfe0c34f57	sram: rewrote read fsm for sram	2021-08-13 14:14:43 +02:00
mwojcik	39509f01d6	aux_controller: sram ported to axi, first attempt	2021-08-13 13:06:10 +02:00
mwojcik	066987bf07	aux_controller: started porting from wb to axi	2021-08-11 14:34:44 +02:00