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aux_controller: fix axi sram data paths

drtio_port
mwojcik 2021-09-29 14:01:06 +02:00
parent 8ab2b3f299
commit f23c6cdb18
1 changed files with 19 additions and 17 deletions
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36
src/gateware/aux_controller.py
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@ -19,17 +19,17 @@ class DRTIOAuxControllerAxi(Module):
tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
wsb = log2_int(len(self.bus.w.data)//8)
aw_decoder = axi.AddressDecoder(self.bus.aw,
[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus.aw),
(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus.aw)],
[(lambda a: a[log2_int(max_packet)] == 0, tx_sdram_if.bus.aw),
(lambda a: a[log2_int(max_packet)] == 1, rx_sdram_if.bus.aw)],
register=True)
ar_decoder = axi.AddressDecoder(self.bus.ar,
[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus.ar),
(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus.ar)],
[(lambda a: a[log2_int(max_packet)] == 0, tx_sdram_if.bus.ar),
(lambda a: a[log2_int(max_packet)] == 1, rx_sdram_if.bus.ar)],
register=True)
# unlike wb, axi address decoder only connects ar/aw lanes,
# the rest must also be connected!
# not quite unlike an address decoder itself.
# connect bus.b with tx.b
self.comb += [tx_sdram_if.bus.b.ready.eq(self.bus.b.ready),
@ -44,20 +44,22 @@ class DRTIOAuxControllerAxi(Module):
tx_sdram_if.bus.w.last.eq(self.bus.w.last),
tx_sdram_if.bus.w.valid.eq(self.bus.w.valid),
self.bus.w.ready.eq(tx_sdram_if.bus.w.ready)]
# connect bus.r with rx.r and tx.r
self.comb += [self.bus.r.id.eq(rx_sdram_if.bus.r.id),
self.bus.r.data.eq(rx_sdram_if.bus.r.data),
self.bus.r.resp.eq(rx_sdram_if.bus.r.resp),
self.bus.r.last.eq(rx_sdram_if.bus.r.last),
self.bus.r.valid.eq(rx_sdram_if.bus.r.valid),
# connect bus.r with rx.r and tx.r w/o data
self.comb += [self.bus.r.id.eq(rx_sdram_if.bus.r.id | tx_sdram_if.bus.r.id),
#self.bus.r.data.eq(rx_sdram_if.bus.r.data | tx_sdram_if.bus.r.data),
self.bus.r.resp.eq(rx_sdram_if.bus.r.resp | tx_sdram_if.bus.r.resp),
self.bus.r.last.eq(rx_sdram_if.bus.r.last | tx_sdram_if.bus.r.last),
self.bus.r.valid.eq(rx_sdram_if.bus.r.valid | tx_sdram_if.bus.r.valid),
rx_sdram_if.bus.r.ready.eq(self.bus.r.ready),
self.bus.r.id.eq(tx_sdram_if.bus.r.id),
self.bus.r.data.eq(tx_sdram_if.bus.r.data),
self.bus.r.resp.eq(tx_sdram_if.bus.r.resp),
self.bus.r.last.eq(tx_sdram_if.bus.r.last),
self.bus.r.valid.eq(tx_sdram_if.bus.r.valid),
tx_sdram_if.bus.r.ready.eq(self.bus.r.ready)]
# connect read data after being masked
masked = [Replicate(rx_sdram_if.bus.r.valid,
len(self.bus.r.data)
) & rx_sdram_if.bus.r.data,
Replicate(tx_sdram_if.bus.r.valid,
len(self.bus.r.data)
) & tx_sdram_if.bus.r.data]
self.comb += self.bus.r.data.eq(reduce(or_, masked))
self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder