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aux_controller: fix class parent

drtio_port
mwojcik 2021-10-04 08:53:38 +02:00
parent b9da4c27fe
commit db1c9d336e
1 changed files with 1 additions and 1 deletions
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src/gateware/aux_controller.py
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@ -72,7 +72,7 @@ class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
@FullMemoryWE()
class DRTIOAuxControllerBare(Module):
class DRTIOAuxControllerBare(_DRTIOAuxControllerBase):
# Barebones version of the AuxController. No SRAM, no decoders.
# add memories manually from tx and rx in target code.
def get_tx_port(self):