forked from M-Labs/artiq-zynq
aux_controller: fix class parent
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@ -72,7 +72,7 @@ class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
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@FullMemoryWE()
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class DRTIOAuxControllerBare(Module):
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class DRTIOAuxControllerBare(_DRTIOAuxControllerBase):
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# Barebones version of the AuxController. No SRAM, no decoders.
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# add memories manually from tx and rx in target code.
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def get_tx_port(self):
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