Robert Jördens
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6a683c712b
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phaser: work around for unreliable transciever init
|
2016-10-16 16:01:23 +02:00 |
Sebastien Bourdeauducq
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d3b274fc4d
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drtio: synchronizer MMCM
|
2016-10-16 17:40:58 +08:00 |
Sebastien Bourdeauducq
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03d3a85e75
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drtio: RX clock alignment and ready
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2016-10-15 18:36:27 +08:00 |
Florent Kermarrec
|
0259c80015
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phaser/kc705: remove transceiver initialization workaround
|
2016-10-14 19:06:43 +02:00 |
Robert Jördens
|
9ba6be8796
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phaser: speed up ad9154_test_status
|
2016-10-14 13:23:14 +02:00 |
Robert Jördens
|
4968de053c
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phaser: update README
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2016-10-14 13:21:54 +02:00 |
Robert Jördens
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4b4fd32e3d
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phaser: add another sawg demo
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2016-10-14 13:21:42 +02:00 |
Robert Jördens
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d16068dd9b
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sawg: absolute phase updates
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2016-10-14 12:42:08 +02:00 |
Robert Jördens
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9b43f09c1d
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phaser: cleanup prbs
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2016-10-14 11:56:10 +02:00 |
Robert Jördens
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b41b9de905
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phaser: tag jesd as clock net
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2016-10-14 10:46:33 +02:00 |
Robert Jördens
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4ea3dea217
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phaser: broad spectrum antibiotics with xilinx false paths
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2016-10-14 10:22:03 +02:00 |
Robert Jördens
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e400f8d672
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phaser: add two more registers before jesd
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2016-10-14 09:54:56 +02:00 |
Robert Jördens
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3c9c42c779
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phaser: drive rtio from jesd-bufg
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2016-10-14 02:26:19 +02:00 |
Robert Jördens
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b9de621557
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phaser: fix comment
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2016-10-14 02:18:58 +02:00 |
Robert Jördens
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2b5a69a80c
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phaser: rm idle_kernel
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2016-10-14 02:18:15 +02:00 |
Robert Jördens
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808874a523
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phaser: drive cd_jesd with BUFG
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2016-10-14 01:57:48 +02:00 |
Robert Jördens
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342d6d756e
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phaser: bypass gtx phalign
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2016-10-14 00:59:53 +02:00 |
Robert Jördens
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89150c9817
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phaser: 10G line rate
|
2016-10-14 00:53:38 +02:00 |
Sebastien Bourdeauducq
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08e4aa3e3f
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drtio: GTX WIP
|
2016-10-14 00:36:13 +08:00 |
Sebastien Bourdeauducq
|
c548a65ec3
|
drtio: clock domains
|
2016-10-14 00:34:59 +08:00 |
Robert Jördens
|
42c6658ffe
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phaser: add some more blinking leds
|
2016-10-13 15:21:27 +02:00 |
Robert Jördens
|
6a456bd7d4
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phaser: feed correct sink (crucial)
|
2016-10-13 15:17:38 +02:00 |
Robert Jördens
|
b1137563b3
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phaser: cleanup dac_setup
|
2016-10-13 15:02:42 +02:00 |
Robert Jördens
|
4c7c479c94
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ad9154: add mirrored bits
|
2016-10-13 15:02:18 +02:00 |
Robert Jördens
|
c8e45ae3f6
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phaser: cleanup jesd phy instantiation a bit
|
2016-10-13 14:43:24 +02:00 |
Robert Jördens
|
01bfe54dde
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phaser: actually enable stpl
|
2016-10-13 14:09:29 +02:00 |
Robert Jördens
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78a41eec8f
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phaser: kc705: syntax
|
2016-10-13 12:38:32 +02:00 |
Florent Kermarrec
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af0e8582a2
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phaser: use new jesd clocking
|
2016-10-13 11:51:06 +02:00 |
David Nadlinger
|
e037d167f4
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language: Add "A" (ampere) as well-known unit for arguments
Signed-off-by: David Nadlinger <code@klickverbot.at>
|
2016-10-13 12:22:01 +08:00 |
Robert Jördens
|
81511feab8
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phaser: README: specify versions
|
2016-10-12 17:13:06 +02:00 |
Robert Jördens
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290498aca0
|
conda: misoc 0.4 (csr)
|
2016-10-12 16:34:19 +02:00 |
Robert Jördens
|
9c8b21b3f4
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phaser: let link settle a bit longer before starting
|
2016-10-12 16:13:34 +02:00 |
Robert Jördens
|
9880b1ebd0
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phaser: update README
|
2016-10-12 16:01:07 +02:00 |
Robert Jördens
|
0d1ed247e2
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phaser: tweak sawg example
|
2016-10-12 16:01:07 +02:00 |
Robert Jördens
|
2d14864c6d
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Revert "phaser: 500 MHz dacclock"
This reverts commit 5f737bef76 .
|
2016-10-12 16:01:07 +02:00 |
Florent Kermarrec
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12b8598b84
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stpl: fix byte ordering
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2016-10-12 15:59:27 +02:00 |
Robert Jördens
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9644a3a362
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ad9154: mix mode addr, digital gain must be on
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2016-10-12 15:00:53 +02:00 |
Robert Jördens
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4376ef5615
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phaser: slow down spi a bit
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2016-10-12 14:37:43 +02:00 |
Robert Jördens
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3f1d96b68d
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phaser: tweak dac_setup
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2016-10-12 14:22:57 +02:00 |
Robert Jördens
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466d1e8304
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phaser: update stpl
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2016-10-12 14:22:21 +02:00 |
Robert Jördens
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5f737bef76
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phaser: 500 MHz dacclock
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2016-10-12 14:03:08 +02:00 |
Robert Jördens
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3b1d5d7eb6
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phaser: verify flags in dac_setup
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2016-10-12 12:19:08 +02:00 |
Robert Jördens
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1117fe191b
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phaser: support core stpl
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2016-10-12 12:03:29 +02:00 |
Robert Jördens
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f515c11f26
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phaser: fix refclk period spec
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2016-10-11 20:13:34 +02:00 |
Robert Jördens
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bae5b73155
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phaser: comment out stpl test
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2016-10-11 19:50:19 +02:00 |
Robert Jördens
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2b1cca2e7e
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phaser: stpl
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2016-10-11 19:29:27 +02:00 |
Sebastien Bourdeauducq
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018f6d1b52
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drtio: implement basic IOT
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2016-10-11 17:59:22 +08:00 |
Robert Jördens
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e4d1f6cf1f
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README_PHASER: update
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2016-10-10 18:49:24 +02:00 |
Robert Jördens
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18d18b6685
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phaser: add sync ttl input for monitoring
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2016-10-10 17:13:23 +02:00 |
Robert Jördens
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f5f7acc1f8
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ttl_simple: add pure Input
(no Tristate for internal signals)
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2016-10-10 17:13:23 +02:00 |