forked from M-Labs/artiq
phaser: update stpl
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@ -1,4 +1,4 @@
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import time
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from jesd204b.transport import seed_to_data
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from artiq.coredevice.ad9154_reg import *
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from artiq.experiment import *
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@ -10,36 +10,41 @@ class Test(EnvExperiment):
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self.setattr_device("ad9154")
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def run(self):
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self.stpl()
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def stpl(self):
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self.ad9154.jesd_stpl(0)
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# short transport layer test
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for i, data in enumerate([0x0123, 0x4567, 0x89ab, 0xcdef]):
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# select dac
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(0) |
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AD9154_SHORT_TPL_TEST_RESET_SET(0) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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# set expected value
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff)
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8)
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# enable stpl
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(1) |
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AD9154_SHORT_TPL_TEST_RESET_SET(0) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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# reset stpl
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(1) |
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AD9154_SHORT_TPL_TEST_RESET_SET(1) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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# release reset stpl
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(1) |
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AD9154_SHORT_TPL_TEST_RESET_SET(0) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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print("c{:d}: {:d}".format(i, self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3)))
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for i in range(4):
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data = seed_to_data(i << 8, True)
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fail = self.stpl(i, data)
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print("channel", i, "FAIL" if fail else "PASS")
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self.ad9154.jesd_stpl(0)
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@kernel
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def stpl(self, i, data):
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# select dac
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(0) |
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AD9154_SHORT_TPL_TEST_RESET_SET(0) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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# set expected value
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff)
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8)
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# enable stpl
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(1) |
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AD9154_SHORT_TPL_TEST_RESET_SET(0) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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# reset stpl
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(1) |
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AD9154_SHORT_TPL_TEST_RESET_SET(1) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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# release reset stpl
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(1) |
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AD9154_SHORT_TPL_TEST_RESET_SET(0) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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return self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3)
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