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stpl: fix byte ordering

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This commit is contained in:
Florent Kermarrec 2016-10-12 15:59:27 +02:00
parent 9644a3a362
commit 12b8598b84
1 changed files with 2 additions and 2 deletions
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4
artiq/examples/phaser/repository/test_ad9154_stpl.py
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@ -27,8 +27,8 @@ class Test(EnvExperiment):
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
# set expected value
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff)
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8)
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, data & 0xff)
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, (data & 0xff00) >> 8)
# enable stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |