forked from M-Labs/artiq
phaser: work around for unreliable transciever init
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0259c80015
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6a683c712b
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@ -34,6 +34,19 @@ class DACSetup(EnvExperiment):
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@kernel
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def run(self):
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# TODO; remove when
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# https://github.com/m-labs/jesd204b/issues/6
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# is resolved
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for i in range(99):
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try:
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self.cfg()
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return
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except:
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pass
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self.cfg()
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@kernel
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def cfg(self):
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self.core.reset()
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self.ad9154.jesd_enable(0)
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self.ad9154.jesd_prbs(0)
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@ -48,6 +61,7 @@ class DACSetup(EnvExperiment):
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self.monitor()
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while not self.ad9154.jesd_ready():
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pass
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self.busywait_us(10000)
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if self.ad9154.dac_read(AD9154_CODEGRPSYNCFLG) != 0x0f:
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raise ValueError("bad CODEGRPSYNCFLG")
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self.core.break_realtime()
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