forked from M-Labs/artiq
phaser: add two more registers before jesd
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@ -511,10 +511,11 @@ class AD9154(Module, AutoCSR):
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x = Signal()
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y = Signal()
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self.sync.jesd += x.eq(~x)
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z = Signal()
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self.sync.jesd += x.eq(~x), z.eq(x == y)
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self.sync.rio_phy += y.eq(x)
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for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
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self.comb += conv.eq(Mux(x != y, Cat(ch.o[:2]), Cat(ch.o[2:])))
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self.sync.jesd += conv.eq(Mux(z, Cat(ch.o[:2]), Cat(ch.o[2:])))
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class Phaser(_NIST_Ions):
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