forked from M-Labs/artiq
phaser: add sync ttl input for monitoring
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@ -44,28 +44,34 @@
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"class": "TTLInOut",
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"arguments": {"channel": 2}
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},
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"sync": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 3}
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},
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"sawg0": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 3, "parallelism": 4}
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"arguments": {"channel_base": 4, "parallelism": 4}
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},
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"sawg1": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 6, "parallelism": 4}
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"arguments": {"channel_base": 7, "parallelism": 4}
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},
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"sawg2": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 9, "parallelism": 4}
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"arguments": {"channel_base": 10, "parallelism": 4}
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},
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"sawg3": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 12, "parallelism": 4}
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"arguments": {"channel_base": 13, "parallelism": 4}
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}
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}
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@ -149,8 +149,10 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.register_kernel_cpu_csrdevice("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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def add_rtio(self, rtio_channels, crg=_RTIOCRG):
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self.submodules.rtio_crg = crg(self.platform, self.crg.cd_sys.clk)
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def add_rtio(self, rtio_channels, rtio_crg=None):
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if rtio_crg is None:
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rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.submodules.rtio_crg = rtio_crg
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self.csr_devices.append("rtio_crg")
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self.submodules.rtio = rtio.RTIO(rtio_channels)
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self.register_kernel_cpu_csrdevice("rtio")
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@ -454,6 +456,7 @@ class AD9154(Module, AutoCSR):
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jesd_sync = Signal()
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self.specials += DifferentialInput(
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sync_pads.p, sync_pads.n, jesd_sync)
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self.jesd_sync = jesd_sync
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ps = JESD204BPhysicalSettings(l=4, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
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@ -510,6 +513,12 @@ class Phaser(_NIST_Ions):
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
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ofifo_depth=2))
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jesd_sync = Signal()
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phy = ttl_simple.Input(jesd_sync)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
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ofifo_depth=2))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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@ -522,11 +531,8 @@ class Phaser(_NIST_Ions):
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels, _PhaserCRG)
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self.add_rtio(rtio_channels, _PhaserCRG(platform, self.crg.cd_sys.clk))
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# jesd_sysref = Signal()
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# self.specials += DifferentialInput(
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# sysref_pads.p, sysref_pads.n, jesd_sysref)
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to_rtio = ClockDomainsRenamer({"sys": "rtio"})
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self.submodules.ad9154 = to_rtio(AD9154(platform, self.rtio_crg))
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self.register_kernel_cpu_csrdevice("ad9154")
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@ -537,6 +543,7 @@ class Phaser(_NIST_Ions):
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"converter{}".format(i))
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# while at 5 GBps, take every second sample... FIXME
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self.comb += conv.eq(Cat(ch.o[::2]))
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self.comb += jesd_sync.eq(self.ad9154.jesd_sync)
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def main():
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@ -170,8 +170,10 @@ The Phaser adapter is an AD9154-FMC-EBZ, a 4 channel 2.4 GHz DAC on an FMC HPC c
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+--------------+------------+--------------+
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| 2 | SYSREF | Input |
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+--------------+------------+--------------+
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| 3 | SYNC | Input |
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+--------------+------------+--------------+
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The SAWG channels start with RTIO channel number 3, each occupying 3 channels.
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The SAWG channels start with RTIO channel number 4, each occupying 3 channels.
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The board has one non-RTIO SPI bus that is accessible through
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:mod:`artiq.coredevice.ad9154`.
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