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6255 Commits

Author SHA1 Message Date
whitequark c4bfc83b38 conda: mark the artiq-build output package as noarch, not toplevel. 
This also changes `noarch: python` to `noarch: generic` since
this is semantically correct; the bitstream/firmware packages
contain no Python code.

Fixes #960.
 2018-03-15 23:17:05 +00:00
whitequark 4b5a78e231 compiler: do not pass files to external tools while they are opened. 
This fixes access violations on Windows that are present both with
input and output files. For some reason, Cygwin-compiled binutils
did not exhibit this problem, but MSYS-compiled binutils do.

Fixes #961.
 2018-03-15 22:21:29 +00:00
whitequark 5cb2602021 artiq_devtool: flash gateware if -g is passed. 2018-03-15 08:33:53 +00:00
whitequark 9ea7d7a804 firmware: allow building without system UART. 2018-03-14 18:34:31 +00:00
whitequark 158ceb0881 artiq_devtool: add kasli target. 2018-03-14 18:13:13 +00:00
Sebastien Bourdeauducq a315ecd10b rtio/ttl_serdes_7series: reset IOSERDES (#958) 2018-03-14 09:01:29 +08:00
Robert Jördens 2fdc180601 dsp/fir: outputs reset_less (pipelined) 2018-03-13 17:11:50 +00:00
Sebastien Bourdeauducq 2edf65f57b drtio: fix satellite minimum_coarse_timestamp clock domain (#947) 2018-03-13 00:20:57 +08:00
Sebastien Bourdeauducq 999ec40e79 bootloader: print gateware ident 2018-03-13 00:11:25 +08:00
Sebastien Bourdeauducq 2caeea6f25 update copyright year 2018-03-13 00:09:13 +08:00
Sebastien Bourdeauducq 1d081ed6c2 drtio: print diagnostic info on satellite write underflow (#947) 2018-03-12 23:41:19 +08:00
Florent Kermarrec eb6e59b44c sayma_rtm: fix serwb timing constraints (was causing the gated clock warning) 2018-03-12 11:25:29 +01:00
Chris Ballance 6dfebd54dd ttl_serdes_7series: use correct IBUFDS_INTERMDISABLE port names 2018-03-12 10:37:33 +08:00
Sebastien Bourdeauducq 44277c5b7e conda: bump migen/misoc 2018-03-11 10:11:42 +08:00
Robert Jördens a04bd5a4fd spi2: xfers take one more cycle until ~busy 2018-03-09 20:48:17 +01:00
Florent Kermarrec 5af4609053 libboard/sdram: limit write leveling scan to "512 - initial dqs taps delay" on ultrascale 2018-03-09 19:06:47 +01:00
Florent Kermarrec a95cd423cc libboard/sdram: add gap for write leveling 2018-03-09 18:53:57 +01:00
Sebastien Bourdeauducq fc3d97f1f7 drtio: remove spurious multichannel transceiver clock constraints 
They used to cause (otherwise harmless) Vivado critical warnings.
 2018-03-09 22:46:27 +08:00
Sebastien Bourdeauducq caf7b14b55 kasli: generate fine RTIO clock in DRTIO targets, separate RTIO channel code 2018-03-09 22:36:16 +08:00
Sebastien Bourdeauducq e65e2421a3 conda: bump migen/misoc 2018-03-09 22:35:40 +08:00
Florent Kermarrec 8f6f83029c libboard/sdram: add write/read leveling scan 2018-03-09 13:50:51 +01:00
Florent Kermarrec b0b13be23b libboard/sdram: rename read_delays to read_leveling 2018-03-09 09:23:20 +01:00
Sebastien Bourdeauducq 3fbcf5f303 drtio: remove TSC correction (#40) 2018-03-09 10:36:17 +08:00
Sebastien Bourdeauducq e38187c760 drtio: increase default underflow margin. Closes #947 2018-03-09 00:49:24 +08:00
Sebastien Bourdeauducq 37f5f0d38d examples: add DMA to Sayma DRTIO 2018-03-09 00:49:24 +08:00
Florent Kermarrec 8475c21c46 firmware/libboard/sdram: kusddrphy now use time mode for odelaye3/idelaye3, now reloading dqs delay_value (500ps) with software 2018-03-08 10:00:00 +01:00
Sebastien Bourdeauducq 8bd15d36c4 drtio: fix error CSR edge detection (#947) 2018-03-08 16:28:25 +08:00
Sebastien Bourdeauducq 0adbbd8ede drtio: reset aux packet gateware after locking to recovered clock 
Closes #949
 2018-03-08 15:41:13 +08:00
Sebastien Bourdeauducq 8bd85caafb examples: fix Sayma DRTIO ref_period 2018-03-08 15:09:33 +08:00
Robert Jördens 37ec97eb28 ad9910/2: add sw invariant only when passed 2018-03-07 21:32:59 +01:00
Robert Jördens 82831a85b6 kasli/opticlock: add eem6 phys 2018-03-07 21:32:59 +01:00
Robert Jördens 5cc1d2a1d3 conda: bump migen, misoc 
* flterm leak
* kasli version
* sayma ddram
* ethernet clocking
* fifo dout reset_less
 2018-03-07 17:17:30 +01:00
Robert Jördens 3a6566f949 rtio: judicious spray with reset_less=True 
Hoping to reduce rst routing difficulty and easier RTIO timing closure.
 2018-03-07 14:57:18 +00:00
Robert Jördens b0282fa855 spi2: reset configuration in rio_phy 2018-03-07 14:42:11 +00:00
Robert Jördens 7afb23e8be runtime: demote dropped and malformed packets msgs to debug 2018-03-07 14:28:21 +01:00
Robert Jördens 4af7600b2d Revert "LaneDistributor: try equivalent spread logic" 
This reverts commit 8b70db5f17.

Just a shot into the dark.
 2018-03-07 11:34:51 +00:00
Robert Jördens a6d1b030c1 RTIO: use TS counter in the correct CD 
artiq/m-labs#938
 2018-03-07 11:34:42 +00:00
Robert Jördens 8b70db5f17 LaneDistributor: try equivalent spread logic 2018-03-07 11:34:42 +00:00
Robert Jördens 2cbd597416 LaneDistributor: style and signal consolidation [NFC] 2018-03-07 11:34:42 +00:00
Sebastien Bourdeauducq 916197c4d7 siphaser: cleanup 2018-03-07 11:15:44 +08:00
Sebastien Bourdeauducq 74d1df3ff0 firmware: implement si5324 skew calibration 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq f7aba6b570 siphaser: fix phase_shift_done CSR 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq acfd9db185 siphaser: minor cleanup 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq e6e5236ce2 firmware: fix si5324 select_recovered_clock 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq 7d98864b31 sayma: enable siphaser 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq c2d2cc2d72 runtime: fix setup_si5324_as_synthesizer 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq a6e29462a8 sayma: enable multilink DRTIO 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq c34d00cbc9 drtio: implement Si5324 phaser gateware and partial firmware support 2018-03-07 10:57:30 +08:00
Robert Jördens 994ceca9ff sayma_amc: disable slave fpga gateware loading 2018-03-06 17:27:43 +01:00
Robert Jördens f4dad87fd9 coredevice: add pcf8574a driver 
I2C IO expander with 8 quasi-bidirectional pins
 2018-03-06 14:27:19 +01:00