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sayma: enable siphaser

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This commit is contained in:
Sebastien Bourdeauducq 2018-03-07 09:43:09 +08:00
parent c2d2cc2d72
commit 7d98864b31
2 changed files with 14 additions and 12 deletions
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12
artiq/gateware/drtio/si_phaser.py
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@ -18,7 +18,7 @@ class SiPhaser7Series(Module, AutoCSR):
# we do not use the crystal reference so that the PFD (f3) frequency
# can be high.
mmcm_freerun_fb = Signal()
mmcm_freerun_output = Signal()
self.mmcm_freerun_output = Signal()
self.specials += \
Instance("MMCME2_BASE",
p_CLKIN1_PERIOD=1e9/125e6,
@ -29,14 +29,14 @@ class SiPhaser7Series(Module, AutoCSR):
o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb,
p_CLKOUT0_DIVIDE_F=5.0, o_CLKOUT0=mmcm_freerun_output,
p_CLKOUT0_DIVIDE_F=5.0, o_CLKOUT0=self.mmcm_freerun_output,
)
# 150MHz to 150MHz with controllable phase shift, VCO @ 1200MHz.
# Inserted between CDR and output to Si, used to correct
# non-determinstic skew of Si5324.
mmcm_ps_fb = Signal()
mmcm_ps_output = Signal()
self.mmcm_ps_output = Signal()
self.specials += \
Instance("MMCME2_ADV",
p_CLKIN1_PERIOD=1e9/150e6,
@ -51,7 +51,7 @@ class SiPhaser7Series(Module, AutoCSR):
o_CLKFBOUT=mmcm_ps_fb, i_CLKFBIN=mmcm_ps_fb,
p_CLKOUT0_USE_FINE_PS="TRUE",
o_CLKOUT0=mmcm_ps_output,
o_CLKOUT0=self.mmcm_ps_output,
i_PSCLK=ClockSignal(),
i_PSEN=self.phase_shift.re,
@ -62,8 +62,8 @@ class SiPhaser7Series(Module, AutoCSR):
si5324_clkin_se = Signal()
self.specials += [
Instance("BUFGMUX",
i_I0=mmcm_freerun_output,
i_I1=mmcm_ps_output,
i_I0=self.mmcm_freerun_output,
i_I1=self.mmcm_ps_output,
i_S=self.switch_clocks.storage,
o_O=si5324_clkin_se
),

14
artiq/gateware/targets/sayma_amc.py
View File

@ -33,6 +33,7 @@ from artiq.gateware import remote_csr
from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple, sawg
from artiq.gateware.drtio.transceiver import gth_ultrascale
from artiq.gateware.drtio.si_phaser import SiPhaser7Series
from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
from artiq.build_soc import build_artiq_soc
@ -432,12 +433,13 @@ class Satellite(BaseSoC):
self.add_memory_group("drtio_aux", ["drtio0_aux"])
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
si5324_clkin = platform.request("si5324_clkin")
self.specials += \
Instance("OBUFDS",
i_I=ClockSignal("rtio_rx0"),
o_O=si5324_clkin.p, o_OB=si5324_clkin.n
)
self.submodules.si_phaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
si5324_clkout_fabric=platform.request("si5324_clkout_fabric")
)
platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]",
mmcm_ps=self.si_phaser.mmcm_ps_output)
self.csr_devices.append("si_phaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")