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drtio: remove TSC correction (#40)

This commit is contained in:
Sebastien Bourdeauducq 2018-03-09 10:36:17 +08:00
parent e38187c760
commit 3fbcf5f303
2 changed files with 5 additions and 13 deletions
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9
artiq/gateware/drtio/rt_controller_master.py
View File

@ -17,7 +17,6 @@ class _CSRs(AutoCSR):
self.protocol_error = CSR(3)
self.tsc_correction = CSRStorage(64)
self.set_time = CSR()
self.underflow_margin = CSRStorage(16, reset=300)
@ -83,13 +82,9 @@ class RTController(Module):
# master RTIO counter and counter synchronization
self.submodules.counter = RTIOCounter(64-fine_ts_width)
self.comb += self.cri.counter.eq(self.counter.value_sys << fine_ts_width)
tsc_correction = Signal(64)
self.csrs.tsc_correction.storage.attr.add("no_retiming")
self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction)
self.comb += [
rt_packet.tsc_value.eq(
self.counter.value_rtio + tsc_correction),
self.cri.counter.eq(self.counter.value_sys << fine_ts_width),
rt_packet.tsc_value.eq(self.counter.value_rtio),
self.csrs.set_time.w.eq(rt_packet.set_time_stb)
]
self.sync += [

9
artiq/gateware/test/drtio/test_full_stack.py
View File

@ -211,7 +211,7 @@ class TestFullStack(unittest.TestCase):
{"sys": test(), "rtio": tb.check_ttls(ttl_changes)}, self.clocks)
self.assertEqual(ttl_changes, correct_ttl_changes)
def test_tsc_error(self):
def test_write_underflow(self):
tb = OutputsTestbench()
def test():
@ -220,11 +220,8 @@ class TestFullStack(unittest.TestCase):
yield from tb.init()
errors = yield from saterr.protocol_error.read()
self.assertEqual(errors, 0)
yield from csrs.tsc_correction.write(100000000)
yield from csrs.set_time.write(1)
for i in range(15):
yield
tb.delay(10000)
yield from csrs.underflow_margin.write(0)
tb.delay(100)
yield from tb.write(0, 1)
for i in range(12):
yield