forked from M-Labs/artiq
ad9910/2: add sw invariant only when passed
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@ -49,7 +49,7 @@ class AD9910:
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:param pll_cp: DDS PLL charge pump setting.
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:param pll_vco: DDS PLL VCO range selection.
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"""
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kernel_invariants = {"chip_select", "cpld", "core", "bus", "sw",
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kernel_invariants = {"chip_select", "cpld", "core", "bus",
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"ftw_per_hz", "pll_n", "pll_cp", "pll_vco"}
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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@ -61,6 +61,7 @@ class AD9910:
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self.chip_select = chip_select
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if sw_device:
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self.sw = dmgr.get(sw_device)
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self.kernel_invariants.add("sw")
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assert 12 <= pll_n <= 127
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self.pll_n = pll_n
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assert self.cpld.refclk/4 <= 60e6
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@ -24,7 +24,7 @@ class AD9912:
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f_ref*pll_n where f_ref is the reference frequency (set in the parent
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Urukul CPLD instance).
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"""
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kernel_invariants = {"chip_select", "cpld", "core", "bus", "sw",
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kernel_invariants = {"chip_select", "cpld", "core", "bus",
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"ftw_per_hz", "sysclk", "pll_n"}
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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@ -36,6 +36,7 @@ class AD9912:
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self.chip_select = chip_select
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if sw_device:
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self.sw = dmgr.get(sw_device)
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self.kernel_invariants.add("sw")
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self.pll_n = pll_n
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self.sysclk = self.cpld.refclk*pll_n
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assert self.sysclk <= 1e9
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