David Nadlinger
ef934ad958
Add test/release notes for command-less controllers
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See eaa1b44b00
for the actual change.
2019-02-07 21:51:15 +00:00
Chris Ballance
eaa1b44b00
ctlmgr: ignore controllers without a "command" field
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Allow controllers to be specified without a "command" field. The user takes
responsibility for ensuring the controller is running: the controller manager
does not attempt to ping the controller. This is useful when one has a common
controller shared between several masters.
2019-02-07 21:50:29 +00:00
hartytp
0ebff04ad7
SUServo: apply bit masks to servo memory writes to prevent overflows
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Signed-off-by: TPH <thomas.harty@physics.ox.ac.uk>
2019-02-07 17:04:11 +01:00
hartytp
f6142816b8
Revert "SUServo: remove references to non-existent a0 parameter" ( #1270 )
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This reverts commit f3aab2b89156bbc1b12f847093a87a8933293df2.
Signed-off-by: TPH <thomas.harty@physics.ox.ac.uk>
2019-02-07 15:57:43 +00:00
hartytp
fe63c9b366
SUServo: remove references to non-existent a0 parameter ( #1268 )
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Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 15:29:32 +00:00
hartytp
df6c1fca2c
SUServo: flake8 [NFC] ( #1267 )
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Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 15:13:44 +00:00
hartytp
87e85bcc14
suservo: fix coefficient data writing
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Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 14:47:11 +01:00
whitequark
d6eb2b023a
compiler: monomorphize casts first, but more carefully.
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This reverts 425cd7851
, which broke the use of casts to define
integer width.
Instead of it, two steps are taken:
* First, literals are monomorphized, leading to predictable result.
* Second, casts are monomorphized, in a top-bottom way. I.e.
consider the expression `int64(round(x))`. If round() was visited
first, the intermediate precision would be 32-bit, which is
clearly undesirable. Therefore, contextual rules should take
priority over non-contextual ones.
Fixes #1252 .
2019-02-07 06:24:32 +00:00
David Nadlinger
0da799fa46
conda: Require recent aiohttp
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artiq_influxdb doesn't work with aiohttp 0.17 (anymore), as the
ClientSession API changed. I have not looked up precisely which
is the first version that works, but 3.x has been out for almost
a year and is available on the Anaconda/conda-forge channels.
2019-02-06 23:39:32 +00:00
Sebastien Bourdeauducq
b56c7cec1e
kasli: use 100MHz RTIO and 800MHz Urukul frequencies on Berkeley target
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Urukul sync is not reliable at 125/1000
2019-02-05 11:24:45 +08:00
Sebastien Bourdeauducq
d0b6f92b11
nix: bump jesd204b
2019-02-04 19:31:09 +08:00
Sebastien Bourdeauducq
2f7364563c
nix: fix breakage introduced by nixpkgs 6f05dea3
2019-02-04 19:28:36 +08:00
Sebastien Bourdeauducq
5a7460a38e
kasli: add sync delays to device_db_berkeley
2019-02-01 22:14:03 +08:00
Sebastien Bourdeauducq
ea431b6982
sayma_rtm: use 150MHz RTIO freq for DDMTD
2019-01-31 20:43:44 +08:00
Sebastien Bourdeauducq
ec230d6560
sayma: move SYSREF DDMTD to the RTM
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Put RTM Si5324 into bypass mode before running.
Needs rework to cut RTM Si5324 reset trace.
Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315.
Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic).
2019-01-31 20:39:33 +08:00
Sebastien Bourdeauducq
8119000982
sayma_rtm_drtio: use Si5324 soft reset
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Needs easy board rework to cut trace at pin 1 of Si5324.
The Si5324 contains an internal pull-up on that pin.
Allows using Si5324 + HMC7043 chips at the same time.
Allows the Si5324 bypass hack for DDMTD experiments on the RTM.
2019-01-31 19:43:54 +08:00
Sebastien Bourdeauducq
82106dcd95
si5324: add bypass function
2019-01-31 19:38:55 +08:00
Sebastien Bourdeauducq
8bbd4207d8
si5324: use consistent bitmask
2019-01-31 19:35:56 +08:00
Sebastien Bourdeauducq
bdb6678cec
nix: bump migen
2019-01-31 15:13:17 +08:00
Sebastien Bourdeauducq
d3c608aaec
jesd204sync: reset and check lock status of DDMTD helper PLL in firmware
2019-01-31 15:11:16 +08:00
Sebastien Bourdeauducq
fa3b40141d
hmc830_7043: document sayma clock muxes
2019-01-31 15:10:11 +08:00
Sebastien Bourdeauducq
ec8560911f
siphaser: bugfixes
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* Fix integer overflow in degree computation
* Add some phase slips after the first transition to get out of the jitter zone and avoid intermittent short windows
2019-01-30 16:56:38 +08:00
Sebastien Bourdeauducq
c591009220
sayma: report TSC phase of SYSREF (TSC LSBs on SYSREF rising edge) in SYSREF sampler
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Better visibility, better diagnostics, allows some changing of SYSREF frequency while keeping the same gateware.
2019-01-29 23:30:01 +08:00
Sebastien Bourdeauducq
9d0d02a561
jesd204sync: increase tolerance for coarse->final target in calibrate_sysref_target
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There is plenty of slack (it only needs to meet timing at the RTIO frequency).
2019-01-29 16:48:55 +08:00
Sebastien Bourdeauducq
ed6aa29897
jesd204sync: print more information on test_slip_ddmtd error
2019-01-29 16:47:29 +08:00
Sebastien Bourdeauducq
2e8decbce3
kasli_sawgmaster: generate a HMC830 clock with Urukul
2019-01-29 15:06:45 +08:00
Sebastien Bourdeauducq
9ae57fd51e
sayma: pass rtio_clk_freq to DDMTD core
2019-01-29 15:06:45 +08:00
Robert Jördens
90c9fa446f
test: add array transfer test
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200 kB/s, more than a factor of 10 slower than the bare string transfer
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-28 14:30:44 +00:00
Sebastien Bourdeauducq
7a5d28b73d
jesd204sync: test SYSREF period
2019-01-28 19:11:38 +08:00
Sebastien Bourdeauducq
1a42e23fb4
jesd204sync: print DDMTD SYSREF final alignment delta
2019-01-28 18:39:16 +08:00
Sebastien Bourdeauducq
eebff6d77f
jesd204sync: fix max_phase_deviation
2019-01-28 18:38:18 +08:00
Sebastien Bourdeauducq
b9e3fab49c
jesd204sync: improve messaging
2019-01-28 18:37:46 +08:00
Sebastien Bourdeauducq
145f08f3fe
jesd204sync: update SYSREF S/H limit deviation tolerance
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Follows the increased DDMTD resolution.
2019-01-28 18:21:31 +08:00
Sebastien Bourdeauducq
ba21dc8498
jesd204sync: improve messaging
2019-01-28 18:08:20 +08:00
Sebastien Bourdeauducq
3acee87df2
firmware: improve DDMTD resolution using dithering/averaging
2019-01-28 16:04:04 +08:00
Sebastien Bourdeauducq
cfe66549ff
jesd204sync: cleanup DDMTD averaging code
2019-01-28 14:14:50 +08:00
Sebastien Bourdeauducq
2b0d63db23
hmc830_7043: support 125MHz RTIO
2019-01-28 13:44:08 +08:00
Sebastien Bourdeauducq
bdd4e52a53
ad9154: support 125MHz RTIO
2019-01-28 13:43:52 +08:00
Sebastien Bourdeauducq
47312e55d3
sayma: set RTIO_FREQUENCY in MasterDAC
2019-01-28 13:43:28 +08:00
Sebastien Bourdeauducq
443d6d8688
sayma_amc: pass RTIO clock frequency to SiPhaser
2019-01-28 09:49:03 +08:00
Sebastien Bourdeauducq
3b6f47886e
firmware: print more info on DDMTD stability error
2019-01-27 23:06:11 +08:00
Sebastien Bourdeauducq
74fdd04622
firmware: test DDMTD stability
2019-01-27 20:39:12 +08:00
Sebastien Bourdeauducq
81b0046f98
ddmtd: add deglitchers
2019-01-27 20:38:41 +08:00
Sebastien Bourdeauducq
8254560577
sayma: properly determine SYSREF coarse calibration target
2019-01-27 16:00:36 +08:00
Sebastien Bourdeauducq
214394e3b0
sayma: reimplement DAC SYSREF autocalibration
2019-01-27 15:28:39 +08:00
Sebastien Bourdeauducq
fdbf1cc2b2
sayma: rework DAC SYSREF margin validation
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Previous code did not work when delay range was not enough for two rotations.
This removes autocalibration, to be done later. Uses hardcoded value for now.
2019-01-27 14:17:54 +08:00
Sebastien Bourdeauducq
7e5c062c2c
firmware: bypass channel divider for HMC7043 DCLK
2019-01-27 11:49:34 +08:00
Sebastien Bourdeauducq
f73ffe44f9
firmware: implement DDMTD-based SYSREF/RTIO alignment (draft)
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Mostly works and usually gets the DAC synchronized at 2.4GHz with Urukul across DRTIO.
Needs cleanup and optimization/characterization.
2019-01-27 09:51:24 +08:00
Sebastien Bourdeauducq
8632b553d2
ddmtd: use IOB register to sample input
2019-01-27 09:50:02 +08:00
Sebastien Bourdeauducq
d1ef036948
kasli_sawgmaster: initialize SAWG phase according to RTIO TSC
2019-01-27 09:49:31 +08:00