Commit Graph

3925 Commits

Author SHA1 Message Date
2b5a69a80c phaser: rm idle_kernel 2016-10-14 02:18:15 +02:00
808874a523 phaser: drive cd_jesd with BUFG 2016-10-14 01:57:48 +02:00
342d6d756e phaser: bypass gtx phalign 2016-10-14 00:59:53 +02:00
89150c9817 phaser: 10G line rate 2016-10-14 00:53:38 +02:00
42c6658ffe phaser: add some more blinking leds 2016-10-13 15:21:27 +02:00
6a456bd7d4 phaser: feed correct sink (crucial) 2016-10-13 15:17:38 +02:00
b1137563b3 phaser: cleanup dac_setup 2016-10-13 15:02:42 +02:00
4c7c479c94 ad9154: add mirrored bits 2016-10-13 15:02:18 +02:00
c8e45ae3f6 phaser: cleanup jesd phy instantiation a bit 2016-10-13 14:43:24 +02:00
01bfe54dde phaser: actually enable stpl 2016-10-13 14:09:29 +02:00
78a41eec8f phaser: kc705: syntax 2016-10-13 12:38:32 +02:00
Florent Kermarrec
af0e8582a2 phaser: use new jesd clocking 2016-10-13 11:51:06 +02:00
David Nadlinger
e037d167f4 language: Add "A" (ampere) as well-known unit for arguments
Signed-off-by: David Nadlinger <code@klickverbot.at>
2016-10-13 12:22:01 +08:00
81511feab8 phaser: README: specify versions 2016-10-12 17:13:06 +02:00
290498aca0 conda: misoc 0.4 (csr) 2016-10-12 16:34:19 +02:00
9c8b21b3f4 phaser: let link settle a bit longer before starting 2016-10-12 16:13:34 +02:00
9880b1ebd0 phaser: update README 2016-10-12 16:01:07 +02:00
0d1ed247e2 phaser: tweak sawg example 2016-10-12 16:01:07 +02:00
2d14864c6d Revert "phaser: 500 MHz dacclock"
This reverts commit 5f737bef76.
2016-10-12 16:01:07 +02:00
Florent Kermarrec
12b8598b84 stpl: fix byte ordering 2016-10-12 15:59:27 +02:00
9644a3a362 ad9154: mix mode addr, digital gain must be on 2016-10-12 15:00:53 +02:00
4376ef5615 phaser: slow down spi a bit 2016-10-12 14:37:43 +02:00
3f1d96b68d phaser: tweak dac_setup 2016-10-12 14:22:57 +02:00
466d1e8304 phaser: update stpl 2016-10-12 14:22:21 +02:00
5f737bef76 phaser: 500 MHz dacclock 2016-10-12 14:03:08 +02:00
3b1d5d7eb6 phaser: verify flags in dac_setup 2016-10-12 12:19:08 +02:00
1117fe191b phaser: support core stpl 2016-10-12 12:03:29 +02:00
f515c11f26 phaser: fix refclk period spec 2016-10-11 20:13:34 +02:00
bae5b73155 phaser: comment out stpl test 2016-10-11 19:50:19 +02:00
2b1cca2e7e phaser: stpl 2016-10-11 19:29:27 +02:00
e4d1f6cf1f README_PHASER: update 2016-10-10 18:49:24 +02:00
18d18b6685 phaser: add sync ttl input for monitoring 2016-10-10 17:13:23 +02:00
f5f7acc1f8 ttl_simple: add pure Input
(no Tristate for internal signals)
2016-10-10 17:13:23 +02:00
e27228fdd5 ad9516: duty cycle correction 2016-10-10 17:13:23 +02:00
Florent Kermarrec
c08caae171 phaser: use qpll 2016-10-10 17:05:42 +02:00
5f7229ef92 ad9154: tweak jesd prbs test 2016-10-09 20:34:15 +02:00
1f93658724 phaser/dac_setup: clear sticky bits, use syncmode=9 2016-10-07 18:54:21 +02:00
89a30b6f7c phaser: error on startup kernel 2016-10-08 00:02:38 +08:00
4e60a6ac71 phaser: tweak sawg example 2016-10-08 00:02:24 +08:00
whitequark
9c3394794e runtime: cap log level at debug. 2016-10-07 14:24:12 +00:00
1157a3a54b ad9514_status: more info 2016-10-07 15:42:46 +02:00
72932fccec phaser: fix sysref for 250 MHz sample rate 2016-10-07 15:40:00 +02:00
cfd2fe8627 phaser: fix fpga deviceclock divider 2016-10-07 13:40:45 +02:00
9b860b26e8 phaser: fix rtio pll inputs 2016-10-07 13:00:42 +02:00
c846e758f1 phaser: fix startup_kernel/ceil 2016-10-07 12:57:38 +02:00
09434ec054 phaser: also adapt rtio_crg 2016-10-07 12:44:22 +02:00
whitequark
4d790b452c runtime: discard unnecessary sections. 2016-10-07 08:30:14 +00:00
whitequark
8eeb6ea1b9 packaging: include runtime.rs in MANIFEST. 2016-10-07 07:53:38 +00:00
Florent Kermarrec
e998a980b3 phaser/startup: use get_configuration_checksum() 2016-10-07 09:00:01 +02:00
Florent Kermarrec
b02a7234f6 phaser: use 125MHz refclk for jesd 2016-10-07 08:59:34 +02:00