forked from M-Labs/artiq
phaser: use 125MHz refclk for jesd
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4390fea437
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b02a7234f6
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@ -1,3 +1,5 @@
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from math import ceil
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from artiq.experiment import *
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from artiq.coredevice.ad9516_reg import *
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@ -47,9 +49,11 @@ class StartupKernel(EnvExperiment):
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self.ad9154.clock_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN |
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2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)
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# FPGA deviceclk, dclk/1
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self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_1 |
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AD9516_DIVIDER_4_BYPASS_2)
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# FPGA deviceclk, dclk/4
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self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)
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self.ad9154.clock_write(AD9516_DIVIDER_0_0,
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(ceil(4/2)-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
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(4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES)
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self.ad9154.clock_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF)
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self.ad9154.clock_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT |
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2*AD9516_OUT9_LVDS_CMOS_OUTPUT_POLARITY |
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@ -460,7 +460,7 @@ class AD9154(Module, AutoCSR):
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ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
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jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_linerate = 5e9
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jesd_refclk_freq = 500e6
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jesd_refclk_freq = 125e6
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rtio_freq = 125*1000*1000
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jesd_phys = [JESD204BPhyTX(
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rtio_crg.refclk, jesd_refclk_freq,
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