forked from M-Labs/artiq
phaser: fix sysref for 250 MHz sample rate
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cfd2fe8627
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@ -57,13 +57,15 @@ class StartupKernel(EnvExperiment):
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2*AD9516_OUT9_LVDS_CMOS_OUTPUT_POLARITY |
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0*AD9516_OUT9_SELECT_LVDS_CMOS)
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# sysref f_data*S/(K*F), dclk/32
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self.ad9154.clock_write(AD9516_DIVIDER_3_0, 15*AD9516_DIVIDER_3_HIGH_CYCLES_1 |
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15*AD9516_DIVIDER_3_LOW_CYCLES_1)
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# sysref f_data*S/(K*F), dclk/64
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self.ad9154.clock_write(AD9516_DIVIDER_3_0, (32//2-1)*AD9516_DIVIDER_3_HIGH_CYCLES_1 |
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(32//2-1)*AD9516_DIVIDER_3_LOW_CYCLES_1)
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self.ad9154.clock_write(AD9516_DIVIDER_3_1, 0*AD9516_DIVIDER_3_PHASE_OFFSET_1 |
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0*AD9516_DIVIDER_3_PHASE_OFFSET_2)
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self.ad9154.clock_write(AD9516_DIVIDER_3_2, (2//2-1)*AD9516_DIVIDER_3_HIGH_CYCLES_2 |
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(2//2-1)*AD9516_DIVIDER_3_LOW_CYCLES_2)
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self.ad9154.clock_write(AD9516_DIVIDER_3_3, 0*AD9516_DIVIDER_3_NOSYNC |
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0*AD9516_DIVIDER_3_BYPASS_1 | 1*AD9516_DIVIDER_3_BYPASS_2)
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0*AD9516_DIVIDER_3_BYPASS_1 | 0*AD9516_DIVIDER_3_BYPASS_2)
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self.ad9154.clock_write(AD9516_DIVIDER_3_4, 1*AD9516_DIVIDER_3_DCCOFF)
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self.ad9154.clock_write(AD9516_OUT6, 1*AD9516_OUT6_LVDS_OUTPUT_CURRENT |
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2*AD9516_OUT6_LVDS_CMOS_OUTPUT_POLARITY |
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