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multiprocessing

smoltcp

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• 2e8d291ee7 running code causes board to fail in an unrecoverable manner master Stewart Mackenzie 2020-01-03 18:07:07 +0800
• 8b025b8644 add .gitignore to ignore the generated target directory Stewart Mackenzie 2020-01-03 18:05:41 +0800
• 9199bb7a16 libboard_zynq::flash: use only 32-bit spi words in program() Astro 2019-12-22 03:14:18 +0100
• da60be38b1 libboard_zynq::flash: move man_start_com(true) into wait_tx_fifo_flush() Astro 2019-12-22 03:13:38 +0100
• 6c4b07e0cf libboard_zynq::flash: syntax Astro 2019-12-22 03:12:53 +0100
• 4439a64974 libboard_zc706: move main.rs into experiments bin crate Astro 2019-12-18 00:06:10 +0100
• cf1983e543 split into lib{register, cortex_a9, board_zynq, board_zc706} crates Astro 2019-12-17 23:35:58 +0100
• 1036ecc0f7 main: add latest experimentation code Astro 2019-12-17 01:07:46 +0100
• a8cb085a25 cortex_a9::mmu: make OCM region cachable Astro 2019-12-17 00:56:18 +0100
• 1ba587ccf9 remove dependency compiler_builtins Astro 2019-12-17 00:30:02 +0100
• 62ecb5095b Cargo.toml: optimize for size Astro 2019-12-17 00:29:08 +0100
• 887627b137 panic: print location info + message Astro 2019-12-17 00:27:20 +0100
• 0adb0d5c51 zynq::flash: remove post-WRDI check Astro 2019-12-16 00:49:29 +0100
• dd0fe054d7 zynq::flash: add working erase(), add barely working program() Astro 2019-12-16 00:48:39 +0100
• 1dbb358a4c zynq::flash::spi_flash_register: doc, add BA Astro 2019-12-16 00:46:53 +0100
• b94afa1581 zynq::flash: add read_reg_until() Astro 2019-12-15 23:52:47 +0100
• 0d1cf04a34 zynq::flash: split into mod transfer Astro 2019-12-15 19:28:55 +0100
• 8a9dde6119 zynq::flash: add consts Astro 2019-12-14 01:57:51 +0100
• 5268839467 zynq::flash: add write_enabled() Astro 2019-12-14 01:56:49 +0100
• 0b9a150255 zynq::flash: abstract SpiFlashRegister Astro 2019-12-14 01:55:17 +0100
• 2d1c8e1f4f zynq::flash: fix txd[123] alignment Astro 2019-12-14 01:07:15 +0100
• e1068af948 zynq::flash: add rdsr1() Astro 2019-12-12 01:02:09 +0100
• 3b3b5dc7c1 zynq::flash: add support for writing 1/2/3-byte words Astro 2019-12-12 00:17:34 +0100
• 70d56d2b28 zynq::flash: doc Astro 2019-12-12 00:13:02 +0100
• b346ea8297 zynq::flash: fix INST_RDCR Astro 2019-12-12 00:11:42 +0100
• e9b80eaef9 zynq::flash: don't send excess data, fixes, refactorings Astro 2019-12-10 02:50:44 +0100
• 0823a74164 zynq::flash: fix rx_thres register Astro 2019-12-10 02:46:25 +0100
• aab82f6843 zynq::flash: enable big endian mode Astro 2019-12-10 02:45:05 +0100
• f3676c945a zynq::flash: flush after instruction Astro 2019-12-07 02:48:55 +0100
• 1e465250f5 zynq::flash: enable/disable spi for every transfer Astro 2019-12-07 02:11:50 +0100
• e37659e4b3 zynq::flash: refactor Astro 2019-12-05 01:15:14 +0100
• 45cc271735 zynq::flash: fix + refactor Astro 2019-12-04 23:56:38 +0100
• cfaa1213e2 zynq::flash: add more initialization Astro 2019-12-03 02:41:49 +0100
• 7107244a6e zynq::flash: start implementing Manual mode Astro 2019-11-30 02:48:39 +0100
• dd3ad3be67 zynq::flash: implement stopping LinearAddressing mode Astro 2019-11-29 23:48:08 +0100
• a8a7f11990 zynq::flash: configure quad i/o fast read mode Astro 2019-11-29 23:37:54 +0100
• 78caca1f04 zynq::flash: setup additional signals Astro 2019-11-28 03:22:26 +0100
• 5642feb824 zynq::flash: add missing config bits to enable addressing mode Astro 2019-11-28 03:02:51 +0100
• a199a5dc7d zynq::flash: add more setup Astro 2019-11-23 01:59:24 +0100
• 3180f1c3f7 zynq::flash: begin driver implementation Astro 2019-11-21 00:14:09 +0100
• 8037042040 zynq::slcr: implement boot_mode bits Astro 2019-11-20 21:31:54 +0100
• 6ffcf7d4a4 ram: lock for concurrent use Astro 2019-11-20 17:25:30 +0100
• 4f8a76e29b stdio: lock for use by core1 Astro 2019-11-20 17:00:57 +0100
• ff41f4dd2d cortex_a9::mutex: restore and fix powersaving behaviour, doc Astro 2019-11-20 16:19:35 +0100
• d89f594ba4 cortex_a9::mutex: use AtomU32, remove powersaving behavior Astro 2019-11-18 02:37:59 +0100
• 4e4ff512d9 add cortex_a9::mutex Astro 2019-11-18 02:13:54 +0100
• 85f29ace6b boot: flush cache-line Astro 2019-11-18 01:13:57 +0100
• ef6d0ff3f1 boot: reset core1 before start Astro 2019-11-18 00:38:03 +0100
• 0bc941d789 main: start_core1 Astro 2019-11-16 00:53:30 +0100
• a416f48af1 main: add empty main_core1() Astro 2019-11-16 00:21:57 +0100
• b6596d930d boot: ACTLR.enable_smp() Astro 2019-11-16 00:12:58 +0100
• 49901d1b8a boot: prepare core1 bootup Astro 2019-11-15 23:54:26 +0100
• 4a1d0fc0c3 zynq::mpcore: add register definitions Björn Stein 2019-11-14 02:11:58 +0100
• 50481b3a80 main: rm obsolete compile feature Astro 2019-11-13 23:33:11 +0100
• b76dc4037d main: change IP address to 192.168.1.51/24 Astro 2019-11-13 16:02:56 +0100
• caa69fda2e main: refactor into boot Astro 2019-11-11 02:43:05 +0100
• 3279aab961 main: refactor into abort, panic, ram Astro 2019-11-11 02:37:06 +0100
• 92c274348f zynq::eth: enable checksum offload Astro 2019-11-11 01:39:07 +0100
• 3eb7fce572 delint Astro 2019-11-11 01:21:30 +0100
• b1472096ba main: change IP address to 192.168.1.28/24 Astro 2019-11-11 01:04:55 +0100
• cb1b5776cd Cargo.lock: update dependencies Astro 2019-11-11 00:45:33 +0100
• 3496755406 update rust + smoltcp Astro 2019-11-11 00:28:46 +0100
• 959bf8a245 zynq::eth: don't check_link_change if link already established Astro 2019-11-11 00:08:05 +0100
• 4d3b2ac7e5 zynq::ddr: use different data_bus_width for targets Astro 2019-11-11 00:06:35 +0100
• cae02947bc zynq::eth: remove all memory barriers Astro 2019-11-10 23:47:56 +0100
• afd96bd887 zynq::clocks: unlock slcr in enable_io() Astro 2019-11-06 23:21:22 +0100
• 261455877d zynq::ddr: fix DDR 3x/2x setup, print clocks Astro 2019-11-06 23:05:29 +0100
• ff96bf903b zynq::ddr: only enable_ddr if no clock yet Astro 2019-11-06 23:04:35 +0100
• d2df5652d0 Revert "zynq: replace unnecessary slcr::unlocked with new" Astro 2019-11-06 22:59:17 +0100
• eb56dda44f zynq::slcr::unlocked: fix comment Astro 2019-11-06 22:58:50 +0100
• 6e50b32e80 openocd: configure SRST for digilent_jtag_smt2_nc + Zynq Sebastien Bourdeauducq 2019-11-05 12:35:59 +0800
• 74c43b3477 zynq::eth::tx: clear entry.word1 for each packet Astro 2019-11-04 02:31:40 +0100
• 99a00e019b zynq::eth: implement phy::extended_status, set clock for link speed Astro 2019-11-04 02:23:27 +0100
• 961e2e1dd0 zynq::{ddr, eth}: fix clock divisor calculation Astro 2019-11-03 02:22:41 +0100
• 04e816d99e zynq::slcr: fix a bitfield index Astro 2019-11-03 02:01:42 +0100
• 6bee1f44f4 zynq: replace unnecessary slcr::unlocked with new Astro 2019-10-31 20:47:05 +0100
• 54e4b9281f main: rewrap linked_list_allocator Astro 2019-10-31 19:20:49 +0100
• f688eb83ab default.nix: update cargoSha256 Astro 2019-10-31 03:19:39 +0100
• 5c62716a99 zynq::eth: switch rx and tx descriptor words to vcell Astro 2019-10-31 03:15:13 +0100
• 1f728686ff rm ram, add linked_list_allocator on ddr Astro 2019-10-31 01:41:10 +0100
• e248d3d3b1 zynq::ddr: optimize memtest Astro 2019-10-31 01:30:04 +0100
• 91bab76ab6 zynq::ddr: fix usable ram size Astro 2019-10-31 01:21:38 +0100
• 43501003f9 openocd/zc706: decimate adapter_khz for reliability Astro 2019-10-31 00:28:19 +0100
• ceeaa6427e zynq::ddr: fix typo Astro 2019-10-28 23:58:25 +0100
• 7cdf6c0918 start implementation of a StaticAllocator Astro 2019-10-28 00:43:57 +0100
• fc39885d3b zynq::ddr: fix clock setup Astro 2019-10-28 00:43:09 +0100
• f199ac68b4 zynq::ddr: don't overwrite slcr.ddr_pll_ctrl Astro 2019-10-27 22:54:34 +0100
• 637bb35f43 zynq::ddr: fix memtest progress calculation Astro 2019-10-27 20:38:35 +0100
• 85bd506132 zynq::ddr: parameters Astro 2019-10-27 20:38:06 +0100
• 27114aec62 zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage Astro 2019-10-27 20:30:38 +0100
• 9b4f07f37c zynq::ddr, main: parameters, memtest Astro 2019-10-25 23:19:34 +0200
• e61d1268ac zynq::slcr: doc, fix Astro 2019-10-25 23:18:18 +0200
• a4d3360a70 zynq::slcr: implement Display for PllStatus Astro 2019-10-25 20:38:10 +0200
• 838434cdec zynq::ddr: wait for init Astro 2019-10-25 19:09:54 +0200
• 4cf5283ba8 zynq::ddr: implement reset_ddrc(), add to main Astro 2019-10-24 01:39:14 +0200
• a8886de067 zynq::ddr: implement configure_iob() Astro 2019-10-24 01:24:12 +0200
• afda48e3fe zynq::ddr: add clock_setup(), calibrate_iob_impedance() Astro 2019-10-22 01:25:35 +0200
• c046bbf8a2 move slcr, clocks, uart, eth into src/zynq/ Astro 2019-10-21 22:19:03 +0200
• 9d725bcf0f zynq::ddr: init with clock setup Astro 2019-10-21 22:12:10 +0200
• 58cf9833cc slcr: implement PllCfg and DdrClkCtrl Astro 2019-10-21 22:10:51 +0200