zynq::eth: remove all memory barriers

They were not the solution.

src/zynq/eth/rx.rs

@@ -3,8 +3,6 @@ use vcell::VolatileCell;
 use crate::{register, register_bit, register_bits, regs::*};
 use super::MTU;
 
-use crate::cortex_a9::asm;
-
 #[derive(Debug)]
 pub enum Error {
     HrespNotOk,
@@ -79,8 +77,6 @@ impl<'a> DescList<'a> {
                 DescWord1::zeroed()
             );
         }
-        // Ensure descriptors get written before they are read.
-        asm::dmb();
 
         DescList {
             // Shorten the list of descriptors to the required number.
@@ -100,7 +96,6 @@ impl<'a> DescList<'a> {
         if entry.word0.read().used() {
             let word1 = entry.word1.read();
             let len = word1.frame_length_lsbs().into();
-            asm::dmb();
             let buffer = &mut self.buffers[self.next][0..len];
 
             self.next += 1;
@@ -128,9 +123,6 @@ pub struct PktRef<'a> {
 
 impl<'a> Drop for PktRef<'a> {
     fn drop(&mut self) {
-        // Ensure that any buffer reads have finished before we
-        // release the buffer to the hardware.
-        asm::dmb();
         self.entry.word0.modify(|_, w| w.used(false));
     }
 }

src/zynq/eth/tx.rs

@@ -1,7 +1,6 @@
 use core::ops::{Deref, DerefMut};
 use vcell::VolatileCell;
 use crate::{register, register_bit, register_bits, regs::*};
-use crate::cortex_a9::asm;
 use super::{MTU, regs};
 
 /// Descriptor entry
@@ -73,8 +72,6 @@ impl<'a> DescList<'a> {
                     .last_buffer(true)
             );
         }
-        // Ensure the descriptor words get written before they are read.
-        asm::dsb();
 
         DescList {
             // Shorten the list of descriptors to the required number.
@@ -123,14 +120,7 @@ pub struct PktRef<'a> {
 
 impl<'a> Drop for PktRef<'a> {
     fn drop(&mut self) {
-        // Ensure that all writes to the buffer have finished before
-        // they are read again.
-        asm::dmb();
         self.entry.word1.modify(|_, w| w.used(false));
-        // Ensure that the descriptor write has finished before it is
-        // read again, and (by DSB, not just DMB) that it has been
-        // written before the register access.
-        asm::dsb();
         if ! self.regs.tx_status.read().tx_go() {
             self.regs.net_ctrl.modify(|_, w|
                                       w.start_tx(true)