Syrostan/FPGA.sch

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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
2021-06-18 16:13:42 +08:00
Sheet 3 8
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
2021-06-16 17:13:34 +08:00
$Comp
L Device:C C18
2021-06-16 17:13:34 +08:00
U 1 1 61137BFE
P 6150 8350
F 0 "C18" H 6265 8396 50 0000 L CNN
F 1 "0.1uF" H 6265 8305 50 0000 L CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6188 8200 50 0001 C CNN
F 3 "~" H 6150 8350 50 0001 C CNN
1 6150 8350
2021-06-16 17:13:34 +08:00
1 0 0 -1
$EndComp
$Comp
L Device:C C20
2021-06-16 17:13:34 +08:00
U 1 1 61141436
P 6500 8350
F 0 "C20" H 6615 8396 50 0000 L CNN
F 1 "10uF" H 6615 8305 50 0000 L CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6538 8200 50 0001 C CNN
F 3 "~" H 6500 8350 50 0001 C CNN
1 6500 8350
2021-06-16 17:13:34 +08:00
1 0 0 -1
$EndComp
$Comp
2021-06-24 15:18:57 +08:00
L Device:R R7
2021-06-16 17:13:34 +08:00
U 1 1 61146472
P 6150 7900
F 0 "R7" V 5943 7900 50 0000 C CNN
F 1 "100" V 6034 7900 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 6080 7900 50 0001 C CNN
F 3 "~" H 6150 7900 50 0001 C CNN
1 6150 7900
2021-06-16 17:13:34 +08:00
-1 0 0 1
$EndComp
$Comp
L Device:C C22
2021-06-16 17:13:34 +08:00
U 1 1 6117399C
P 6900 8350
F 0 "C22" H 7015 8396 50 0000 L CNN
F 1 "0.1uF" H 7015 8305 50 0000 L CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6938 8200 50 0001 C CNN
F 3 "~" H 6900 8350 50 0001 C CNN
1 6900 8350
2021-06-16 17:13:34 +08:00
1 0 0 -1
$EndComp
$Comp
L Device:C C23
2021-06-16 17:13:34 +08:00
U 1 1 611739A2
P 7250 8350
F 0 "C23" H 7365 8396 50 0000 L CNN
F 1 "10uF" H 7365 8305 50 0000 L CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 7288 8200 50 0001 C CNN
F 3 "~" H 7250 8350 50 0001 C CNN
1 7250 8350
2021-06-16 17:13:34 +08:00
1 0 0 -1
$EndComp
$Comp
L Device:R R8
2021-06-16 17:13:34 +08:00
U 1 1 611739A8
P 6900 7900
F 0 "R8" V 6693 7900 50 0000 C CNN
F 1 "100" V 6784 7900 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 6830 7900 50 0001 C CNN
F 3 "~" H 6900 7900 50 0001 C CNN
1 6900 7900
2021-06-16 17:13:34 +08:00
-1 0 0 1
$EndComp
Wire Wire Line
7250 8100 7250 8200
2021-06-16 17:13:34 +08:00
Wire Wire Line
6900 8100 7250 8100
2021-06-16 17:13:34 +08:00
Wire Wire Line
6900 8500 6900 8600
2021-06-16 17:13:34 +08:00
Wire Wire Line
6900 8600 7250 8600
2021-06-16 17:13:34 +08:00
Wire Wire Line
7250 8600 7250 8500
2021-06-16 17:13:34 +08:00
Wire Wire Line
6500 8500 6500 8600
2021-06-16 17:13:34 +08:00
Wire Wire Line
6500 8600 6150 8600
2021-06-16 17:13:34 +08:00
Wire Wire Line
6150 8600 6150 8500
2021-06-16 17:13:34 +08:00
Wire Wire Line
6150 8100 6500 8100
2021-06-16 17:13:34 +08:00
Wire Wire Line
6500 8100 6500 8200
2021-06-16 17:13:34 +08:00
Wire Wire Line
6150 8100 6150 8200
2021-06-16 17:13:34 +08:00
$Comp
L power:+1V2 #PWR015
2021-06-16 17:13:34 +08:00
U 1 1 61193177
P 6150 7650
F 0 "#PWR015" H 6150 7500 50 0001 C CNN
F 1 "+1V2" V 6165 7778 50 0000 L CNN
F 2 "" H 6150 7650 50 0001 C CNN
F 3 "" H 6150 7650 50 0001 C CNN
1 6150 7650
2021-06-16 17:13:34 +08:00
1 0 0 -1
$EndComp
$Comp
L power:+1V2 #PWR016
2021-06-16 17:13:34 +08:00
U 1 1 61194D75
P 6900 7650
F 0 "#PWR016" H 6900 7500 50 0001 C CNN
F 1 "+1V2" V 6915 7778 50 0000 L CNN
F 2 "" H 6900 7650 50 0001 C CNN
F 3 "" H 6900 7650 50 0001 C CNN
1 6900 7650
2021-06-16 17:13:34 +08:00
1 0 0 -1
$EndComp
Wire Wire Line
6900 7750 6900 7650
2021-06-16 17:13:34 +08:00
Wire Wire Line
6150 7750 6150 7650
Text Label 6550 8100 0 50 ~ 0
2021-06-16 17:13:34 +08:00
VCCPLL0
Text Label 7300 8100 0 50 ~ 0
2021-06-16 17:13:34 +08:00
VCCPLL1
Text Label 6550 8600 0 50 ~ 0
2021-06-16 17:13:34 +08:00
GNDPLL0
Text Label 7300 8600 0 50 ~ 0
2021-06-16 17:13:34 +08:00
GNDPLL1
Wire Wire Line
6550 8100 6500 8100
Connection ~ 6500 8100
2021-06-16 17:13:34 +08:00
Wire Wire Line
6550 8600 6500 8600
Connection ~ 6500 8600
2021-06-16 17:13:34 +08:00
Wire Wire Line
7300 8100 7250 8100
Connection ~ 7250 8100
2021-06-16 17:13:34 +08:00
Wire Wire Line
7300 8600 7250 8600
Connection ~ 7250 8600
2021-06-24 15:18:57 +08:00
$Comp
L Power_Protection:PRTR5V0U2X D1
U 1 1 610B0EF3
P 3100 7950
F 0 "D1" H 3644 7996 50 0000 L CNN
F 1 "PRTR5V0U2X" H 3644 7905 50 0000 L CNN
F 2 "Package_TO_SOT_SMD:SOT-143" H 3160 7950 50 0001 C CNN
F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 3160 7950 50 0001 C CNN
1 3100 7950
2021-06-24 15:18:57 +08:00
1 0 0 -1
$EndComp
Text Label 5700 4850 0 50 ~ 0
2021-06-24 15:18:57 +08:00
I2C_0_SDA
Text Label 5700 5650 0 50 ~ 0
2021-06-24 15:18:57 +08:00
I2C_0_SCL
Text Label 5700 5350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
I2C_1_SDA
Text Label 5700 5950 0 50 ~ 0
2021-06-24 15:18:57 +08:00
I2C_1_SCL
$Comp
L Power_Protection:PRTR5V0U2X D2
U 1 1 6137EFAD
P 4200 7950
F 0 "D2" H 4744 7996 50 0000 L CNN
F 1 "PRTR5V0U2X" H 4744 7905 50 0000 L CNN
F 2 "Package_TO_SOT_SMD:SOT-143" H 4260 7950 50 0001 C CNN
F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 4260 7950 50 0001 C CNN
1 4200 7950
2021-06-24 15:18:57 +08:00
1 0 0 -1
$EndComp
2021-06-16 17:13:34 +08:00
Wire Wire Line
6900 8050 6900 8100
Connection ~ 6900 8100
2021-06-16 17:13:34 +08:00
Wire Wire Line
6900 8100 6900 8200
2021-06-16 17:13:34 +08:00
Wire Wire Line
6150 8050 6150 8100
Connection ~ 6150 8100
2021-06-24 15:18:57 +08:00
$Comp
L Power_Protection:PRTR5V0U2X D3
U 1 1 6150DB5A
P 5300 7950
F 0 "D3" H 5844 7996 50 0000 L CNN
F 1 "PRTR5V0U2X" H 5844 7905 50 0000 L CNN
F 2 "Package_TO_SOT_SMD:SOT-143" H 5360 7950 50 0001 C CNN
F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 5360 7950 50 0001 C CNN
1 5300 7950
2021-06-24 15:18:57 +08:00
1 0 0 -1
$EndComp
Text HLabel 5750 4850 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_IIC_SDA
Text HLabel 5750 5650 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_IIC_SCL
Text HLabel 5750 5350 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_IIC_SDA
Text HLabel 5750 5950 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_IIC_SCL
2021-06-16 17:13:34 +08:00
Wire Wire Line
5650 4850 5750 4850
2021-06-16 17:13:34 +08:00
Wire Wire Line
5650 5650 5750 5650
2021-06-16 17:13:34 +08:00
Wire Wire Line
5650 5350 5750 5350
2021-06-16 17:13:34 +08:00
Wire Wire Line
5650 5950 5750 5950
2021-06-16 17:13:34 +08:00
Wire Wire Line
3100 7400 3100 7450
2021-06-16 17:13:34 +08:00
Wire Wire Line
4200 7450 4200 7400
2021-06-16 17:13:34 +08:00
Wire Wire Line
3100 8450 3100 8500
2021-06-16 17:13:34 +08:00
Wire Wire Line
5300 8500 5300 8450
2021-06-16 17:13:34 +08:00
Wire Wire Line
4200 8450 4200 8500
Text Label 2600 8050 3 50 ~ 0
2021-06-24 15:18:57 +08:00
I2C_0_SDA
Text Label 3600 8050 3 50 ~ 0
2021-06-24 15:18:57 +08:00
I2C_0_SCL
Text Label 3700 8050 3 50 ~ 0
2021-06-24 15:18:57 +08:00
I2C_1_SDA
Text Label 4700 8050 3 50 ~ 0
2021-06-24 15:18:57 +08:00
I2C_1_SCL
Text Label 4800 8050 3 50 ~ 0
2021-06-24 15:18:57 +08:00
I2C_2_SDA
Text Label 5800 8050 3 50 ~ 0
2021-06-24 15:18:57 +08:00
I2C_2_SCL
2021-06-16 17:13:34 +08:00
Wire Wire Line
5800 8050 5800 7950
2021-06-16 17:13:34 +08:00
Wire Wire Line
4800 7950 4800 8050
2021-06-16 17:13:34 +08:00
Wire Wire Line
4700 8050 4700 7950
2021-06-16 17:13:34 +08:00
Wire Wire Line
3700 8050 3700 7950
2021-06-16 17:13:34 +08:00
Wire Wire Line
3600 8050 3600 7950
2021-06-16 17:13:34 +08:00
Wire Wire Line
2600 8050 2600 7950
Text HLabel 3750 3450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_A0
Text HLabel 3750 2750 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_A3
Text HLabel 3750 3150 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_A4
Text HLabel 3750 3650 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_A5
Text HLabel 3750 4250 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_A6
Text HLabel 3750 2550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D0
Text HLabel 3750 2950 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D1
Text HLabel 3750 2650 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D2
Text HLabel 3750 2450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D3
Text HLabel 3750 5550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D4
Text HLabel 3750 5350 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D5
Text HLabel 3750 6250 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D6
Text HLabel 3750 5850 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D7
Text HLabel 3750 4950 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D9
Text HLabel 3750 5050 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D10
Text HLabel 3750 4750 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D11
Text HLabel 3750 4450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D12
Text HLabel 3750 4150 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D13
Text HLabel 3750 4350 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D14
Text HLabel 3750 4050 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_D15
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 3450 3700 3450
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 2750 3700 2750
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 3150 3700 3150
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 3650 3700 3650
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 4250 3700 4250
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 2550 3700 2550
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 2950 3700 2950
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 2650 3700 2650
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 2450 3700 2450
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 5550 3700 5550
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 5350 3700 5350
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 6250 3700 6250
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 5850 3700 5850
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 4950 3700 4950
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 5050 3700 5050
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 4750 3700 4750
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 4450 3700 4450
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 4150 3700 4150
2021-06-16 17:13:34 +08:00
Wire Wire Line
3750 4350 3700 4350
Wire Wire Line
3750 4050 3700 4050
2021-06-16 17:13:34 +08:00
Wire Wire Line
3100 7400 4200 7400
2021-06-16 17:13:34 +08:00
Wire Wire Line
5300 7400 5300 7450
Connection ~ 4200 7400
2021-06-16 17:13:34 +08:00
Wire Wire Line
4200 7400 5300 7400
2021-06-16 17:13:34 +08:00
Wire Wire Line
5300 8500 4200 8500
Connection ~ 4200 8500
2021-06-16 17:13:34 +08:00
Wire Wire Line
4200 8500 3100 8500
2021-06-16 17:13:34 +08:00
$Comp
L power:GND #PWR014
2021-06-24 15:18:57 +08:00
U 1 1 62303F6D
P 4200 8550
F 0 "#PWR014" H 4200 8300 50 0001 C CNN
F 1 "GND" H 4205 8377 50 0000 C CNN
F 2 "" H 4200 8550 50 0001 C CNN
F 3 "" H 4200 8550 50 0001 C CNN
1 4200 8550
2021-06-24 15:18:57 +08:00
1 0 0 -1
2021-06-16 17:13:34 +08:00
$EndComp
Wire Wire Line
4200 7350 4200 7400
Text HLabel 7700 5550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_CSBSEL0
Text HLabel 7700 5650 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_CSBSEL1
Text HLabel 7700 6150 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_SPI_SDO
Text HLabel 7700 6050 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_SPI_SDI
Text HLabel 7700 5850 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_SPI_SS
Text HLabel 7700 5950 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_SPI_SCK
2021-06-16 17:13:34 +08:00
Wire Wire Line
7700 5550 7650 5550
2021-06-16 17:13:34 +08:00
Wire Wire Line
7700 5650 7650 5650
2021-06-16 17:13:34 +08:00
Wire Wire Line
7700 5850 7650 5850
2021-06-16 17:13:34 +08:00
Wire Wire Line
7700 5950 7650 5950
2021-06-16 17:13:34 +08:00
Wire Wire Line
7700 6050 7650 6050
2021-06-16 17:13:34 +08:00
Wire Wire Line
7700 6150 7650 6150
2021-06-16 17:13:34 +08:00
Wire Wire Line
7650 6350 7700 6350
2021-06-16 17:13:34 +08:00
Wire Wire Line
7650 6450 7700 6450
Text HLabel 7700 6350 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_CDONE
Text HLabel 7700 6450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_CRESET
2021-06-16 17:13:34 +08:00
Wire Wire Line
7800 8050 7750 8050
2021-06-16 17:13:34 +08:00
Wire Wire Line
7750 7950 7800 7950
2021-06-16 17:13:34 +08:00
$Comp
L power:+3V3 #PWR018
2021-06-24 15:18:57 +08:00
U 1 1 627E070D
P 8400 6900
F 0 "#PWR018" H 8400 6750 50 0001 C CNN
F 1 "+3V3" H 8415 7073 50 0000 C CNN
F 2 "" H 8400 6900 50 0001 C CNN
F 3 "" H 8400 6900 50 0001 C CNN
1 8400 6900
2021-06-24 15:18:57 +08:00
1 0 0 -1
2021-06-16 17:13:34 +08:00
$EndComp
$Comp
L power:+3V3 #PWR017
2021-06-24 15:18:57 +08:00
U 1 1 627E243D
P 7750 8150
F 0 "#PWR017" H 7750 8000 50 0001 C CNN
F 1 "+3V3" H 7765 8323 50 0000 C CNN
F 2 "" H 7750 8150 50 0001 C CNN
F 3 "" H 7750 8150 50 0001 C CNN
1 7750 8150
2021-06-24 15:18:57 +08:00
-1 0 0 1
2021-06-16 17:13:34 +08:00
$EndComp
$Comp
L power:GND #PWR019
2021-06-24 15:18:57 +08:00
U 1 1 627E46CA
P 8400 8400
F 0 "#PWR019" H 8400 8150 50 0001 C CNN
F 1 "GND" H 8405 8227 50 0000 C CNN
F 2 "" H 8400 8400 50 0001 C CNN
F 3 "" H 8400 8400 50 0001 C CNN
1 8400 8400
2021-06-24 15:18:57 +08:00
1 0 0 -1
2021-06-16 17:13:34 +08:00
$EndComp
Wire Wire Line
8400 8350 8400 8400
2021-06-16 17:13:34 +08:00
Wire Wire Line
7750 7950 7750 8050
Connection ~ 7750 8050
2021-06-16 17:13:34 +08:00
Wire Wire Line
7750 8050 7750 8150
Text Label 7650 5950 0 50 ~ 0
2021-06-24 15:18:57 +08:00
SPI_SCK
Text Label 7650 5850 0 50 ~ 0
2021-06-24 15:18:57 +08:00
SPI_SS
Text Label 7650 6150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
SPI_MOSI
Text Label 7650 6050 0 50 ~ 0
2021-06-24 15:18:57 +08:00
SPI_MISO
Text Label 7750 7750 2 50 ~ 0
2021-06-24 15:18:57 +08:00
SPI_SCK
Text Label 7750 7850 2 50 ~ 0
2021-06-24 15:18:57 +08:00
SPI_SS
Text Label 7750 7650 2 50 ~ 0
2021-06-24 15:18:57 +08:00
SPI_MOSI
Text Label 9050 7650 0 50 ~ 0
2021-06-24 15:18:57 +08:00
SPI_MISO
Wire Wire Line
9050 7650 9000 7650
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 7650 7800 7650
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 7750 7800 7750
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 7850 7800 7850
Text Label 7650 6350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
CDONE
Text Label 7650 6450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
CRESET
Text Label 10450 8000 2 50 ~ 0
2021-06-24 15:18:57 +08:00
SPI_SS
Text Label 10450 7900 2 50 ~ 0
2021-06-24 15:18:57 +08:00
CRESET
Text Label 10450 7800 2 50 ~ 0
2021-06-24 15:18:57 +08:00
CDONE
Wire Wire Line
10450 7900 10550 7900
2021-06-24 15:18:57 +08:00
Wire Wire Line
10550 8000 10450 8000
2021-06-24 15:18:57 +08:00
Wire Wire Line
10550 7800 10450 7800
2021-06-24 15:18:57 +08:00
Wire Wire Line
11050 7900 10950 7900
2021-06-24 15:18:57 +08:00
$Comp
L power:+3V3 #PWR024
2021-06-24 15:18:57 +08:00
U 1 1 62D9CC4C
P 11050 7900
F 0 "#PWR024" H 11050 7750 50 0001 C CNN
F 1 "+3V3" V 11065 8028 50 0000 L CNN
F 2 "" H 11050 7900 50 0001 C CNN
F 3 "" H 11050 7900 50 0001 C CNN
1 11050 7900
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
Wire Wire Line
10950 7900 10950 8000
Connection ~ 10950 7900
2021-06-24 15:18:57 +08:00
Wire Wire Line
10850 7900 10950 7900
2021-06-24 15:18:57 +08:00
Wire Wire Line
10950 8000 10850 8000
2021-06-24 15:18:57 +08:00
Wire Wire Line
10950 7800 10950 7900
2021-06-24 15:18:57 +08:00
Wire Wire Line
10850 7800 10950 7800
2021-06-24 15:18:57 +08:00
$Comp
L Device:R R59
2021-06-24 15:18:57 +08:00
U 1 1 62CE70DD
P 10700 8000
F 0 "R59" V 10700 8150 50 0000 C CNN
F 1 "10k" V 10700 8000 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10630 8000 50 0001 C CNN
F 3 "~" H 10700 8000 50 0001 C CNN
1 10700 8000
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R58
2021-06-24 15:18:57 +08:00
U 1 1 62CBFB4D
P 10700 7900
F 0 "R58" V 10700 8050 50 0000 C CNN
F 1 "10k" V 10700 7900 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10630 7900 50 0001 C CNN
F 3 "~" H 10700 7900 50 0001 C CNN
1 10700 7900
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R57
2021-06-24 15:18:57 +08:00
U 1 1 62C9E4F5
P 10700 7800
F 0 "R57" V 10700 7950 50 0000 C CNN
F 1 "10k" V 10700 7800 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10630 7800 50 0001 C CNN
F 3 "~" H 10700 7800 50 0001 C CNN
1 10700 7800
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
Text HLabel 5750 5850 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IIC_SDA
Text HLabel 5750 5550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IIC_SCL
Wire Wire Line
5650 5850 5750 5850
2021-06-24 15:18:57 +08:00
Wire Wire Line
5650 5550 5750 5550
Text HLabel 5750 3250 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_ADC_D1
Text HLabel 5750 3150 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_ADC_D2
Text HLabel 5750 2750 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_ADC_D3
Text HLabel 5750 2350 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_ADC_D4
Text HLabel 5750 2550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_ADC_D5
Text HLabel 5750 1950 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_ADC_D6
Text HLabel 5750 1550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_ADC_D7
Text HLabel 5750 1450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_ADC_CLK
Wire Wire Line
5750 3250 5650 3250
Wire Wire Line
5750 3150 5650 3150
2021-06-24 15:18:57 +08:00
Wire Wire Line
5750 2750 5650 2750
2021-06-24 15:18:57 +08:00
Wire Wire Line
5750 2350 5650 2350
2021-06-24 15:18:57 +08:00
Wire Wire Line
5750 2550 5650 2550
2021-06-24 15:18:57 +08:00
Wire Wire Line
5750 1950 5650 1950
2021-06-24 15:18:57 +08:00
Wire Wire Line
5750 1550 5650 1550
2021-06-24 15:18:57 +08:00
Wire Wire Line
5750 1450 5650 1450
Text HLabel 3750 1950 2 50 Input ~ 0
FPGA_FSMC_NWE
Text HLabel 3750 1450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_NOE
Text HLabel 3750 1750 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_NBL0
Text HLabel 3750 1550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_NBL1
Text HLabel 3750 1150 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_NL
Text HLabel 3750 2050 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_CLK
Text HLabel 3750 1250 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_FSMC_NWAIT
Wire Wire Line
3750 1950 3700 1950
2021-06-24 15:18:57 +08:00
Wire Wire Line
3700 1450 3750 1450
2021-06-24 15:18:57 +08:00
Wire Wire Line
3750 1750 3700 1750
2021-06-24 15:18:57 +08:00
Wire Wire Line
3700 1550 3750 1550
2021-06-24 15:18:57 +08:00
Wire Wire Line
3750 1150 3700 1150
2021-06-24 15:18:57 +08:00
Wire Wire Line
3700 2050 3750 2050
2021-06-24 15:18:57 +08:00
Wire Wire Line
3750 1250 3700 1250
Text HLabel 7750 2650 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO2
Text HLabel 7750 3750 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO3
Text HLabel 7750 1950 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO4
Text HLabel 7750 3550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO5
Text HLabel 7750 2050 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO6
Text HLabel 7750 4050 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO7
Text HLabel 7750 1850 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO8
Text HLabel 7750 4450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO9
Text HLabel 7750 1650 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO10
Text HLabel 7750 4550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO11
Text HLabel 7750 1450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO12
Text HLabel 7750 4950 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO13
Text HLabel 7750 1250 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO14
Text HLabel 7750 4750 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_IO15
Wire Wire Line
7750 2650 7650 2650
2021-06-24 15:18:57 +08:00
Wire Wire Line
7650 3750 7750 3750
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 1950 7650 1950
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 3550 7650 3550
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 2050 7650 2050
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 4050 7650 4050
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 1850 7650 1850
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 4450 7650 4450
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 1650 7650 1650
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 4550 7650 4550
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 1450 7650 1450
2021-06-24 15:18:57 +08:00
Wire Wire Line
7750 4950 7650 4950
2021-06-24 15:18:57 +08:00
Wire Wire Line
7650 1250 7750 1250
2021-06-24 15:18:57 +08:00
Wire Wire Line
7650 4750 7750 4750
2021-06-24 15:18:57 +08:00
$Comp
L TestAutomation:ICE40HX8K-CT256 U4
2021-06-24 15:18:57 +08:00
U 1 1 623CB106
P 3000 3750
F 0 "U4" H 3107 6719 50 0000 C CNN
F 1 "ICE40HX8K-CT256" H 3107 6628 50 0000 C CNN
F 2 "TestAutomation:iCE40-BGA256C80P16X16_1400X1400X170" V 2700 3050 50 0001 L BNN
F 3 "" H 3000 3750 50 0001 L BNN
F 4 "3.4" V 2900 3650 50 0001 L BNN "PART_REV"
F 5 "IPC-7351B" V 2800 3500 50 0001 L BNN "STANDARD"
F 6 "Lattice Semiconductor" V 3000 3350 50 0001 L BNN "MANUFACTURER"
1 3000 3750
2021-06-24 15:18:57 +08:00
1 0 0 -1
$EndComp
$Comp
L TestAutomation:ICE40HX8K-CT256 U4
2021-06-24 15:18:57 +08:00
U 2 1 6253F35F
P 4950 3750
F 0 "U4" H 5057 6730 50 0000 C CNN
F 1 "ICE40HX8K-CT256" H 5057 6639 50 0000 C CNN
F 2 "TestAutomation:iCE40-BGA256C80P16X16_1400X1400X170" V 4650 3050 50 0001 L BNN
F 3 "" H 4950 3750 50 0001 L BNN
F 4 "3.4" V 4850 3650 50 0001 L BNN "PART_REV"
F 5 "IPC-7351B" V 4750 3500 50 0001 L BNN "STANDARD"
F 6 "Lattice Semiconductor" V 4950 3350 50 0001 L BNN "MANUFACTURER"
2 4950 3750
2021-06-24 15:18:57 +08:00
1 0 0 -1
$EndComp
$Comp
L TestAutomation:ICE40HX8K-CT256 U4
2021-06-24 15:18:57 +08:00
U 3 1 62546FE8
P 6950 3750
F 0 "U4" H 7057 6720 50 0000 C CNN
F 1 "ICE40HX8K-CT256" H 7057 6629 50 0000 C CNN
F 2 "TestAutomation:iCE40-BGA256C80P16X16_1400X1400X170" V 6650 3050 50 0001 L BNN
F 3 "" H 6950 3750 50 0001 L BNN
F 4 "3.4" V 6850 3650 50 0001 L BNN "PART_REV"
F 5 "IPC-7351B" V 6750 3500 50 0001 L BNN "STANDARD"
F 6 "Lattice Semiconductor" V 6950 3350 50 0001 L BNN "MANUFACTURER"
3 6950 3750
2021-06-24 15:18:57 +08:00
1 0 0 -1
$EndComp
$Comp
L TestAutomation:ICE40HX8K-CT256 U4
2021-06-24 15:18:57 +08:00
U 4 1 62557659
P 8950 3950
F 0 "U4" H 9057 6918 50 0000 C CNN
F 1 "ICE40HX8K-CT256" H 9057 6827 50 0000 C CNN
F 2 "TestAutomation:iCE40-BGA256C80P16X16_1400X1400X170" V 8650 3250 50 0001 L BNN
F 3 "" H 8950 3950 50 0001 L BNN
F 4 "3.4" V 8850 3850 50 0001 L BNN "PART_REV"
F 5 "IPC-7351B" V 8750 3700 50 0001 L BNN "STANDARD"
F 6 "Lattice Semiconductor" V 8950 3550 50 0001 L BNN "MANUFACTURER"
4 8950 3950
2021-06-24 15:18:57 +08:00
1 0 0 -1
$EndComp
$Comp
L Device:Q_NPN_BEC Q?
U 1 1 61C9A1CC
P 12000 7950
2021-06-24 15:18:57 +08:00
AR Path="/60E3407A/61C9A1CC" Ref="Q?" Part="1"
AR Path="/60C0E996/61C9A1CC" Ref="Q1" Part="1"
F 0 "Q1" H 12190 7996 50 0000 L CNN
F 1 "PMBT3904" H 12190 7905 50 0000 L CNN
F 2 "Package_TO_SOT_SMD:SOT-23" H 12200 8050 50 0001 C CNN
F 3 "~" H 12000 7950 50 0001 C CNN
1 12000 7950
2021-06-25 18:15:56 +08:00
0 1 1 0
2021-06-24 15:18:57 +08:00
$EndComp
Wire Wire Line
12300 7750 13100 7750
2021-06-24 15:18:57 +08:00
Wire Wire Line
12100 7750 12000 7750
2021-06-24 15:18:57 +08:00
$Comp
L Device:R_Small R84
2021-06-24 15:18:57 +08:00
U 1 1 623C0DC2
P 12200 7750
F 0 "R84" H 12259 7796 50 0000 L CNN
F 1 "10k" H 12259 7705 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 12200 7750 50 0001 C CNN
F 3 "~" H 12200 7750 50 0001 C CNN
1 12200 7750
2021-06-25 18:15:56 +08:00
0 1 1 0
2021-06-24 15:18:57 +08:00
$EndComp
$Comp
L Device:R_Small R86
2021-06-24 15:18:57 +08:00
U 1 1 61ED30A4
P 12700 8050
F 0 "R86" H 12759 8096 50 0000 L CNN
F 1 "220" H 12759 8005 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 12700 8050 50 0001 C CNN
F 3 "~" H 12700 8050 50 0001 C CNN
1 12700 8050
2021-06-25 18:15:56 +08:00
0 1 1 0
2021-06-24 15:18:57 +08:00
$EndComp
$Comp
L Device:LED D4
U 1 1 61B7C071
P 12400 8050
F 0 "D4" V 12439 7932 50 0000 R CNN
F 1 "LED_FPGA" V 12348 7932 50 0000 R CNN
F 2 "LED_SMD:LED_0603_1608Metric" H 12400 8050 50 0001 C CNN
F 3 "~" H 12400 8050 50 0001 C CNN
1 12400 8050
2021-06-25 18:15:56 +08:00
1 0 0 -1
2021-06-24 15:18:57 +08:00
$EndComp
$Comp
L power:+3V3 #PWR034
2021-06-24 15:18:57 +08:00
U 1 1 61B96C01
P 12950 8050
F 0 "#PWR034" H 12950 7900 50 0001 C CNN
F 1 "+3V3" H 12965 8223 50 0000 C CNN
F 2 "" H 12950 8050 50 0001 C CNN
F 3 "" H 12950 8050 50 0001 C CNN
1 12950 8050
2021-06-25 18:15:56 +08:00
0 1 1 0
2021-06-24 15:18:57 +08:00
$EndComp
$Comp
L power:GND #PWR025
2021-06-24 15:18:57 +08:00
U 1 1 61C1A434
P 11650 8050
F 0 "#PWR025" H 11650 7800 50 0001 C CNN
F 1 "GND" H 11655 7877 50 0000 C CNN
F 2 "" H 11650 8050 50 0001 C CNN
F 3 "" H 11650 8050 50 0001 C CNN
1 11650 8050
2021-06-25 18:15:56 +08:00
0 1 1 0
2021-06-24 15:18:57 +08:00
$EndComp
Wire Wire Line
12800 8050 12850 8050
2021-06-24 15:18:57 +08:00
Wire Wire Line
12600 8050 12550 8050
2021-06-24 15:18:57 +08:00
Wire Wire Line
12250 8050 12200 8050
2021-06-24 15:18:57 +08:00
Wire Wire Line
11800 8050 11700 8050
2021-06-24 15:18:57 +08:00
Wire Wire Line
11700 8050 11650 8050
Connection ~ 11700 8050
2021-06-24 15:18:57 +08:00
Wire Wire Line
11700 7600 11700 8050
2021-06-24 15:18:57 +08:00
Wire Wire Line
4200 8500 4200 8550
2021-06-24 15:18:57 +08:00
$Comp
L Switch:SW_Push SW?
U 1 1 6100CA18
P 12300 7600
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/6100CA18" Ref="SW?" Part="1"
AR Path="/60C0E996/6100CA18" Ref="SW1" Part="1"
F 0 "SW1" H 12300 7885 50 0000 C CNN
F 1 "SW_FPGA" H 12300 7794 50 0000 C CNN
F 2 "Button_Switch_SMD:SW_SPST_SKQG_WithoutStem" H 12300 7800 50 0001 C CNN
F 3 "~" H 12300 7800 50 0001 C CNN
1 12300 7600
2021-06-25 18:15:56 +08:00
1 0 0 -1
2021-06-24 15:18:57 +08:00
$EndComp
$Comp
L Device:R_Small R85
2021-06-24 15:18:57 +08:00
U 1 1 61AE7ED5
P 12700 7950
F 0 "R85" H 12759 7996 50 0000 L CNN
F 1 "10k" H 12759 7905 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 12700 7950 50 0001 C CNN
F 3 "~" H 12700 7950 50 0001 C CNN
1 12700 7950
2021-06-25 18:15:56 +08:00
0 -1 -1 0
2021-06-24 15:18:57 +08:00
$EndComp
Wire Wire Line
13000 7600 12550 7600
2021-06-24 15:18:57 +08:00
Wire Wire Line
12800 7950 12850 7950
2021-06-24 15:18:57 +08:00
Wire Wire Line
12850 7950 12850 8050
2021-06-24 15:18:57 +08:00
Wire Wire Line
12850 8050 12950 8050
Connection ~ 12850 8050
2021-06-24 15:18:57 +08:00
Wire Wire Line
12600 7950 12550 7950
2021-06-24 15:18:57 +08:00
Wire Wire Line
12550 7950 12550 7600
Connection ~ 12550 7600
2021-06-24 15:18:57 +08:00
Wire Wire Line
12550 7600 12500 7600
2021-06-24 15:18:57 +08:00
Wire Wire Line
12100 7600 11700 7600
2021-06-24 15:18:57 +08:00
$Comp
L TestAutomation:ICE40HX8K-CT256 U4
2021-06-24 15:18:57 +08:00
U 5 1 6256A27C
P 12050 3800
F 0 "U4" H 12157 6667 50 0000 C CNN
F 1 "ICE40HX8K-CT256" H 12157 6576 50 0000 C CNN
F 2 "TestAutomation:iCE40-BGA256C80P16X16_1400X1400X170" V 11750 3100 50 0001 L BNN
F 3 "" H 12050 3800 50 0001 L BNN
F 4 "3.4" V 11950 3700 50 0001 L BNN "PART_REV"
F 5 "IPC-7351B" V 11850 3550 50 0001 L BNN "STANDARD"
F 6 "Lattice Semiconductor" V 12050 3400 50 0001 L BNN "MANUFACTURER"
5 12050 3800
2021-06-24 15:18:57 +08:00
1 0 0 -1
$EndComp
$Comp
L Device:R R43
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E88
P 10350 5150
AR Path="/60C0E996/60DF7E88" Ref="R43" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E88" Ref="R?" Part="1"
F 0 "R43" V 10143 5150 50 0000 C CNN
F 1 "140/1%" V 10234 5150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 5150 50 0001 C CNN
F 3 "~" H 10350 5150 50 0001 C CNN
1 10350 5150
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R44
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E82
P 10350 5250
AR Path="/60C0E996/60DF7E82" Ref="R44" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E82" Ref="R?" Part="1"
F 0 "R44" V 10143 5250 50 0000 C CNN
F 1 "140/1%" V 10234 5250 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 5250 50 0001 C CNN
F 3 "~" H 10350 5250 50 0001 C CNN
1 10350 5250
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R77
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E7C
P 11150 5150
AR Path="/60C0E996/60DF7E7C" Ref="R77" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E7C" Ref="R?" Part="1"
F 0 "R77" V 10943 5150 50 0000 C CNN
F 1 "100/1%" V 11034 5150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 5150 50 0001 C CNN
F 3 "~" H 11150 5150 50 0001 C CNN
1 11150 5150
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
Wire Wire Line
11350 5250 11350 5150
2021-06-24 15:18:57 +08:00
Wire Wire Line
11350 5150 11300 5150
Text HLabel 10550 5150 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM2_1_N
Wire Wire Line
10500 5150 11000 5150
2021-06-24 15:18:57 +08:00
Wire Wire Line
10500 5250 11350 5250
Text HLabel 10550 5250 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM2_1_P
$Comp
L Device:R R45
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E6E
P 10350 5350
AR Path="/60C0E996/60DF7E6E" Ref="R45" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E6E" Ref="R?" Part="1"
F 0 "R45" V 10143 5350 50 0000 C CNN
F 1 "140/1%" V 10234 5350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 5350 50 0001 C CNN
F 3 "~" H 10350 5350 50 0001 C CNN
1 10350 5350
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R46
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E68
P 10350 5450
AR Path="/60C0E996/60DF7E68" Ref="R46" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E68" Ref="R?" Part="1"
F 0 "R46" V 10143 5450 50 0000 C CNN
F 1 "140/1%" V 10234 5450 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 5450 50 0001 C CNN
F 3 "~" H 10350 5450 50 0001 C CNN
1 10350 5450
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R78
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E62
P 11150 5350
AR Path="/60C0E996/60DF7E62" Ref="R78" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E62" Ref="R?" Part="1"
F 0 "R78" V 10943 5350 50 0000 C CNN
F 1 "100/1%" V 11034 5350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 5350 50 0001 C CNN
F 3 "~" H 11150 5350 50 0001 C CNN
1 11150 5350
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
Wire Wire Line
11350 5450 11350 5350
2021-06-24 15:18:57 +08:00
Wire Wire Line
11350 5350 11300 5350
Text HLabel 10550 5350 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM2_2_N
Wire Wire Line
10500 5350 11000 5350
2021-06-24 15:18:57 +08:00
Wire Wire Line
10500 5450 11350 5450
Text HLabel 10550 5450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM2_2_P
$Comp
L Device:R R47
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E56
P 10350 5550
AR Path="/60C0E996/60DF7E56" Ref="R47" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E56" Ref="R?" Part="1"
F 0 "R47" V 10143 5550 50 0000 C CNN
F 1 "140/1%" V 10234 5550 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 5550 50 0001 C CNN
F 3 "~" H 10350 5550 50 0001 C CNN
1 10350 5550
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R48
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E50
P 10350 5650
AR Path="/60C0E996/60DF7E50" Ref="R48" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E50" Ref="R?" Part="1"
F 0 "R48" V 10143 5650 50 0000 C CNN
F 1 "140/1%" V 10234 5650 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 5650 50 0001 C CNN
F 3 "~" H 10350 5650 50 0001 C CNN
1 10350 5650
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R79
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E4A
P 11150 5550
AR Path="/60C0E996/60DF7E4A" Ref="R79" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E4A" Ref="R?" Part="1"
F 0 "R79" V 10943 5550 50 0000 C CNN
F 1 "100/1%" V 11034 5550 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 5550 50 0001 C CNN
F 3 "~" H 11150 5550 50 0001 C CNN
1 11150 5550
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
Wire Wire Line
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2021-06-24 15:18:57 +08:00
Wire Wire Line
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2021-06-24 15:18:57 +08:00
FPGA_EEM2_3_N
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2021-06-24 15:18:57 +08:00
Wire Wire Line
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Text HLabel 10550 5650 2 50 Input ~ 0
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FPGA_EEM2_3_P
$Comp
L Device:R R49
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E3A
P 10350 5750
AR Path="/60C0E996/60DF7E3A" Ref="R49" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E3A" Ref="R?" Part="1"
F 0 "R49" V 10143 5750 50 0000 C CNN
F 1 "140/1%" V 10234 5750 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 5750 50 0001 C CNN
F 3 "~" H 10350 5750 50 0001 C CNN
1 10350 5750
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R50
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E34
P 10350 5850
AR Path="/60C0E996/60DF7E34" Ref="R50" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E34" Ref="R?" Part="1"
F 0 "R50" V 10143 5850 50 0000 C CNN
F 1 "140/1%" V 10234 5850 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 5850 50 0001 C CNN
F 3 "~" H 10350 5850 50 0001 C CNN
1 10350 5850
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R80
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E2E
P 11150 5750
AR Path="/60C0E996/60DF7E2E" Ref="R80" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E2E" Ref="R?" Part="1"
F 0 "R80" V 10943 5750 50 0000 C CNN
F 1 "100/1%" V 11034 5750 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 5750 50 0001 C CNN
F 3 "~" H 11150 5750 50 0001 C CNN
1 11150 5750
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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FPGA_EEM2_4_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 5850 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM2_4_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R51
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E20
P 10350 5950
AR Path="/60C0E996/60DF7E20" Ref="R51" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E20" Ref="R?" Part="1"
F 0 "R51" V 10143 5950 50 0000 C CNN
F 1 "140/1%" V 10234 5950 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 5950 50 0001 C CNN
F 3 "~" H 10350 5950 50 0001 C CNN
1 10350 5950
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R52
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E1A
P 10350 6050
AR Path="/60C0E996/60DF7E1A" Ref="R52" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E1A" Ref="R?" Part="1"
F 0 "R52" V 10143 6050 50 0000 C CNN
F 1 "140/1%" V 10234 6050 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 6050 50 0001 C CNN
F 3 "~" H 10350 6050 50 0001 C CNN
1 10350 6050
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R81
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E14
P 11150 5950
AR Path="/60C0E996/60DF7E14" Ref="R81" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E14" Ref="R?" Part="1"
F 0 "R81" V 10943 5950 50 0000 C CNN
F 1 "100/1%" V 11034 5950 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 5950 50 0001 C CNN
F 3 "~" H 11150 5950 50 0001 C CNN
1 11150 5950
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 5950 2 50 Input ~ 0
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FPGA_EEM2_5_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 6050 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM2_5_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R53
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E06
P 10350 6150
AR Path="/60C0E996/60DF7E06" Ref="R53" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E06" Ref="R?" Part="1"
F 0 "R53" V 10143 6150 50 0000 C CNN
F 1 "140/1%" V 10234 6150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 6150 50 0001 C CNN
F 3 "~" H 10350 6150 50 0001 C CNN
1 10350 6150
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R54
2021-06-24 15:18:57 +08:00
U 1 1 60DF7E00
P 10350 6250
AR Path="/60C0E996/60DF7E00" Ref="R54" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7E00" Ref="R?" Part="1"
F 0 "R54" V 10143 6250 50 0000 C CNN
F 1 "140/1%" V 10234 6250 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 6250 50 0001 C CNN
F 3 "~" H 10350 6250 50 0001 C CNN
1 10350 6250
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R82
2021-06-24 15:18:57 +08:00
U 1 1 60DF7DFA
P 11150 6150
AR Path="/60C0E996/60DF7DFA" Ref="R82" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7DFA" Ref="R?" Part="1"
F 0 "R82" V 10943 6150 50 0000 C CNN
F 1 "100/1%" V 11034 6150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 6150 50 0001 C CNN
F 3 "~" H 11150 6150 50 0001 C CNN
1 11150 6150
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 6150 2 50 Input ~ 0
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FPGA_EEM2_6_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 6250 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM2_6_P
$Comp
L Device:R R55
2021-06-24 15:18:57 +08:00
U 1 1 60DF7DEE
P 10350 6350
AR Path="/60C0E996/60DF7DEE" Ref="R55" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7DEE" Ref="R?" Part="1"
F 0 "R55" V 10143 6350 50 0000 C CNN
F 1 "140/1%" V 10234 6350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 6350 50 0001 C CNN
F 3 "~" H 10350 6350 50 0001 C CNN
1 10350 6350
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R56
2021-06-24 15:18:57 +08:00
U 1 1 60DF7DE8
P 10350 6450
AR Path="/60C0E996/60DF7DE8" Ref="R56" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7DE8" Ref="R?" Part="1"
F 0 "R56" V 10143 6450 50 0000 C CNN
F 1 "140/1%" V 10234 6450 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 6450 50 0001 C CNN
F 3 "~" H 10350 6450 50 0001 C CNN
1 10350 6450
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R83
2021-06-24 15:18:57 +08:00
U 1 1 60DF7DE2
P 11150 6350
AR Path="/60C0E996/60DF7DE2" Ref="R83" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7DE2" Ref="R?" Part="1"
F 0 "R83" V 10943 6350 50 0000 C CNN
F 1 "100/1%" V 11034 6350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 6350 50 0001 C CNN
F 3 "~" H 11150 6350 50 0001 C CNN
1 11150 6350
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 6350 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM2_7_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 6450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM2_7_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R41
2021-06-24 15:18:57 +08:00
U 1 1 60DF7DD2
P 10350 4950
AR Path="/60C0E996/60DF7DD2" Ref="R41" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7DD2" Ref="R?" Part="1"
F 0 "R41" V 10143 4950 50 0000 C CNN
F 1 "140/1%" V 10234 4950 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 4950 50 0001 C CNN
F 3 "~" H 10350 4950 50 0001 C CNN
1 10350 4950
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R42
2021-06-24 15:18:57 +08:00
U 1 1 60DF7DCC
P 10350 5050
AR Path="/60C0E996/60DF7DCC" Ref="R42" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7DCC" Ref="R?" Part="1"
F 0 "R42" V 10143 5050 50 0000 C CNN
F 1 "140/1%" V 10234 5050 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 5050 50 0001 C CNN
F 3 "~" H 10350 5050 50 0001 C CNN
1 10350 5050
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R76
2021-06-24 15:18:57 +08:00
U 1 1 60DF7DC6
P 11150 4950
AR Path="/60C0E996/60DF7DC6" Ref="R76" Part="1"
2021-06-24 15:18:57 +08:00
AR Path="/60C2FDBB/60DF7DC6" Ref="R?" Part="1"
F 0 "R76" V 10943 4950 50 0000 C CNN
F 1 "100/1%" V 11034 4950 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 4950 50 0001 C CNN
F 3 "~" H 11150 4950 50 0001 C CNN
1 11150 4950
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 4950 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM2_0_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 5050 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM2_0_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R27
2021-06-24 15:18:57 +08:00
U 1 1 60CE4C56
P 10350 3350
F 0 "R27" V 10143 3350 50 0000 C CNN
F 1 "140/1%" V 10234 3350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 3350 50 0001 C CNN
F 3 "~" H 10350 3350 50 0001 C CNN
1 10350 3350
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R28
2021-06-24 15:18:57 +08:00
U 1 1 60CE4C50
P 10350 3450
F 0 "R28" V 10143 3450 50 0000 C CNN
F 1 "140/1%" V 10234 3450 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 3450 50 0001 C CNN
F 3 "~" H 10350 3450 50 0001 C CNN
1 10350 3450
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R69
2021-06-24 15:18:57 +08:00
U 1 1 60CE4C4A
P 11150 3350
F 0 "R69" V 10943 3350 50 0000 C CNN
F 1 "100/1%" V 11034 3350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 3350 50 0001 C CNN
F 3 "~" H 11150 3350 50 0001 C CNN
1 11150 3350
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 3350 2 50 Input ~ 0
2021-06-16 17:13:34 +08:00
FPGA_EEM1_1_N
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 3450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_1_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R29
2021-06-24 15:18:57 +08:00
U 1 1 60CE4C3C
P 10350 3550
F 0 "R29" V 10143 3550 50 0000 C CNN
F 1 "140/1%" V 10234 3550 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 3550 50 0001 C CNN
F 3 "~" H 10350 3550 50 0001 C CNN
1 10350 3550
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R30
2021-06-24 15:18:57 +08:00
U 1 1 60CE4C36
P 10350 3650
F 0 "R30" V 10143 3650 50 0000 C CNN
F 1 "140/1%" V 10234 3650 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 3650 50 0001 C CNN
F 3 "~" H 10350 3650 50 0001 C CNN
1 10350 3650
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R70
2021-06-24 15:18:57 +08:00
U 1 1 60CE4C30
P 11150 3550
F 0 "R70" V 10943 3550 50 0000 C CNN
F 1 "100/1%" V 11034 3550 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 3550 50 0001 C CNN
F 3 "~" H 11150 3550 50 0001 C CNN
1 11150 3550
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 3550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_2_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 3650 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_2_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R31
2021-06-24 15:18:57 +08:00
U 1 1 60CE4C24
P 10350 3750
F 0 "R31" V 10143 3750 50 0000 C CNN
F 1 "140/1%" V 10234 3750 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 3750 50 0001 C CNN
F 3 "~" H 10350 3750 50 0001 C CNN
1 10350 3750
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R32
2021-06-24 15:18:57 +08:00
U 1 1 60CE4C1E
P 10350 3850
F 0 "R32" V 10143 3850 50 0000 C CNN
F 1 "140/1%" V 10234 3850 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 3850 50 0001 C CNN
F 3 "~" H 10350 3850 50 0001 C CNN
1 10350 3850
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R71
2021-06-24 15:18:57 +08:00
U 1 1 60CE4C18
P 11150 3750
F 0 "R71" V 10943 3750 50 0000 C CNN
F 1 "100/1%" V 11034 3750 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 3750 50 0001 C CNN
F 3 "~" H 11150 3750 50 0001 C CNN
1 11150 3750
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 3750 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_3_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 3850 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_3_P
$Comp
L Device:R R33
2021-06-24 15:18:57 +08:00
U 1 1 60CE4C08
P 10350 3950
F 0 "R33" V 10143 3950 50 0000 C CNN
F 1 "140/1%" V 10234 3950 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 3950 50 0001 C CNN
F 3 "~" H 10350 3950 50 0001 C CNN
1 10350 3950
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R34
2021-06-24 15:18:57 +08:00
U 1 1 60CE4C02
P 10350 4050
F 0 "R34" V 10143 4050 50 0000 C CNN
F 1 "140/1%" V 10234 4050 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 4050 50 0001 C CNN
F 3 "~" H 10350 4050 50 0001 C CNN
1 10350 4050
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R72
2021-06-24 15:18:57 +08:00
U 1 1 60CE4BFC
P 11150 3950
F 0 "R72" V 10943 3950 50 0000 C CNN
F 1 "100/1%" V 11034 3950 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 3950 50 0001 C CNN
F 3 "~" H 11150 3950 50 0001 C CNN
1 11150 3950
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 3950 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_4_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
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Text HLabel 10550 4050 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_4_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R35
2021-06-24 15:18:57 +08:00
U 1 1 60CE4BEE
P 10350 4150
F 0 "R35" V 10143 4150 50 0000 C CNN
F 1 "140/1%" V 10234 4150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 4150 50 0001 C CNN
F 3 "~" H 10350 4150 50 0001 C CNN
1 10350 4150
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R36
2021-06-24 15:18:57 +08:00
U 1 1 60CE4BE8
P 10350 4250
F 0 "R36" V 10143 4250 50 0000 C CNN
F 1 "140/1%" V 10234 4250 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 4250 50 0001 C CNN
F 3 "~" H 10350 4250 50 0001 C CNN
1 10350 4250
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R73
2021-06-24 15:18:57 +08:00
U 1 1 60CE4BE2
P 11150 4150
F 0 "R73" V 10943 4150 50 0000 C CNN
F 1 "100/1%" V 11034 4150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 4150 50 0001 C CNN
F 3 "~" H 11150 4150 50 0001 C CNN
1 11150 4150
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 4150 11300 4150
Text HLabel 10550 4150 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_5_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 4250 11350 4250
Text HLabel 10550 4250 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_5_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R37
2021-06-24 15:18:57 +08:00
U 1 1 60CE4BD4
P 10350 4350
F 0 "R37" V 10143 4350 50 0000 C CNN
F 1 "140/1%" V 10234 4350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 4350 50 0001 C CNN
F 3 "~" H 10350 4350 50 0001 C CNN
1 10350 4350
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R38
2021-06-24 15:18:57 +08:00
U 1 1 60CE4BCE
P 10350 4450
F 0 "R38" V 10143 4450 50 0000 C CNN
F 1 "140/1%" V 10234 4450 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 4450 50 0001 C CNN
F 3 "~" H 10350 4450 50 0001 C CNN
1 10350 4450
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R74
2021-06-24 15:18:57 +08:00
U 1 1 60CE4BC8
P 11150 4350
F 0 "R74" V 10943 4350 50 0000 C CNN
F 1 "100/1%" V 11034 4350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 4350 50 0001 C CNN
F 3 "~" H 11150 4350 50 0001 C CNN
1 11150 4350
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
11350 4450 11350 4350
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 4350 11300 4350
Text HLabel 10550 4350 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_6_N
Wire Wire Line
10500 4350 11000 4350
2021-06-24 15:18:57 +08:00
Wire Wire Line
10500 4450 11350 4450
Text HLabel 10550 4450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_6_P
$Comp
L Device:R R39
2021-06-24 15:18:57 +08:00
U 1 1 60CE4BBC
P 10350 4550
F 0 "R39" V 10143 4550 50 0000 C CNN
F 1 "140/1%" V 10234 4550 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 4550 50 0001 C CNN
F 3 "~" H 10350 4550 50 0001 C CNN
1 10350 4550
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R40
2021-06-24 15:18:57 +08:00
U 1 1 60CE4BB6
P 10350 4650
F 0 "R40" V 10143 4650 50 0000 C CNN
F 1 "140/1%" V 10234 4650 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 4650 50 0001 C CNN
F 3 "~" H 10350 4650 50 0001 C CNN
1 10350 4650
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R75
2021-06-24 15:18:57 +08:00
U 1 1 60CE4BB0
P 11150 4550
F 0 "R75" V 10943 4550 50 0000 C CNN
F 1 "100/1%" V 11034 4550 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 4550 50 0001 C CNN
F 3 "~" H 11150 4550 50 0001 C CNN
1 11150 4550
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 4650 11350 4550
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 4550 11300 4550
Text HLabel 10550 4550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_7_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
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2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 4650 11350 4650
Text HLabel 10550 4650 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_7_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R25
2021-06-24 15:18:57 +08:00
U 1 1 60CE4BA0
P 10350 3150
F 0 "R25" V 10143 3150 50 0000 C CNN
F 1 "140/1%" V 10234 3150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 3150 50 0001 C CNN
F 3 "~" H 10350 3150 50 0001 C CNN
1 10350 3150
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R26
2021-06-24 15:18:57 +08:00
U 1 1 60CE4B9A
P 10350 3250
F 0 "R26" V 10143 3250 50 0000 C CNN
F 1 "140/1%" V 10234 3250 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 3250 50 0001 C CNN
F 3 "~" H 10350 3250 50 0001 C CNN
1 10350 3250
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R68
2021-06-24 15:18:57 +08:00
U 1 1 60CE4B94
P 11150 3150
F 0 "R68" V 10943 3150 50 0000 C CNN
F 1 "100/1%" V 11034 3150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 3150 50 0001 C CNN
F 3 "~" H 11150 3150 50 0001 C CNN
1 11150 3150
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
11350 3250 11350 3150
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 3150 11300 3150
Text HLabel 10550 3150 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_0_N
Wire Wire Line
10500 3150 11000 3150
2021-06-24 15:18:57 +08:00
Wire Wire Line
10500 3250 11350 3250
Text HLabel 10550 3250 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM1_0_P
$Comp
L Device:R R11
2021-06-24 15:18:57 +08:00
U 1 1 61390A34
P 10350 1550
F 0 "R11" V 10143 1550 50 0000 C CNN
F 1 "140/1%" V 10234 1550 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 1550 50 0001 C CNN
F 3 "~" H 10350 1550 50 0001 C CNN
1 10350 1550
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R12
2021-06-24 15:18:57 +08:00
U 1 1 613952D3
P 10350 1650
F 0 "R12" V 10143 1650 50 0000 C CNN
F 1 "140/1%" V 10234 1650 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 1650 50 0001 C CNN
F 3 "~" H 10350 1650 50 0001 C CNN
1 10350 1650
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R61
2021-06-24 15:18:57 +08:00
U 1 1 613AEA51
P 11150 1550
F 0 "R61" V 10943 1550 50 0000 C CNN
F 1 "100/1%" V 11034 1550 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 1550 50 0001 C CNN
F 3 "~" H 11150 1550 50 0001 C CNN
1 11150 1550
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 1650 11350 1550
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 1550 11300 1550
Text HLabel 10550 1550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_1_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 1550 11000 1550
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 1650 11350 1650
Text HLabel 10550 1650 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_1_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R13
2021-06-24 15:18:57 +08:00
U 1 1 614580DC
P 10350 1750
F 0 "R13" V 10143 1750 50 0000 C CNN
F 1 "140/1%" V 10234 1750 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 1750 50 0001 C CNN
F 3 "~" H 10350 1750 50 0001 C CNN
1 10350 1750
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R14
2021-06-24 15:18:57 +08:00
U 1 1 614580E2
P 10350 1850
F 0 "R14" V 10143 1850 50 0000 C CNN
F 1 "140/1%" V 10234 1850 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 1850 50 0001 C CNN
F 3 "~" H 10350 1850 50 0001 C CNN
1 10350 1850
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R62
2021-06-24 15:18:57 +08:00
U 1 1 614580E8
P 11150 1750
F 0 "R62" V 10943 1750 50 0000 C CNN
F 1 "100/1%" V 11034 1750 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 1750 50 0001 C CNN
F 3 "~" H 11150 1750 50 0001 C CNN
1 11150 1750
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
11350 1850 11350 1750
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 1750 11300 1750
Text HLabel 10550 1750 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_2_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 1750 11000 1750
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 1850 11350 1850
Text HLabel 10550 1850 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_2_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R15
2021-06-24 15:18:57 +08:00
U 1 1 6145E7A3
P 10350 1950
F 0 "R15" V 10143 1950 50 0000 C CNN
F 1 "140/1%" V 10234 1950 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 1950 50 0001 C CNN
F 3 "~" H 10350 1950 50 0001 C CNN
1 10350 1950
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R16
2021-06-24 15:18:57 +08:00
U 1 1 6145E7A9
P 10350 2050
F 0 "R16" V 10143 2050 50 0000 C CNN
F 1 "140/1%" V 10234 2050 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 2050 50 0001 C CNN
F 3 "~" H 10350 2050 50 0001 C CNN
1 10350 2050
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R63
2021-06-24 15:18:57 +08:00
U 1 1 6145E7AF
P 11150 1950
F 0 "R63" V 10943 1950 50 0000 C CNN
F 1 "100/1%" V 11034 1950 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 1950 50 0001 C CNN
F 3 "~" H 11150 1950 50 0001 C CNN
1 11150 1950
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
11350 2050 11350 1950
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 1950 11300 1950
Text HLabel 10550 1950 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_3_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 1950 11000 1950
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 2050 11350 2050
Text HLabel 10550 2050 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_3_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R17
2021-06-24 15:18:57 +08:00
U 1 1 614C2784
P 10350 2150
F 0 "R17" V 10143 2150 50 0000 C CNN
F 1 "140/1%" V 10234 2150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 2150 50 0001 C CNN
F 3 "~" H 10350 2150 50 0001 C CNN
1 10350 2150
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R18
2021-06-24 15:18:57 +08:00
U 1 1 614C278A
P 10350 2250
F 0 "R18" V 10143 2250 50 0000 C CNN
F 1 "140/1%" V 10234 2250 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 2250 50 0001 C CNN
F 3 "~" H 10350 2250 50 0001 C CNN
1 10350 2250
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R64
2021-06-24 15:18:57 +08:00
U 1 1 614C2790
P 11150 2150
F 0 "R64" V 10943 2150 50 0000 C CNN
F 1 "100/1%" V 11034 2150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 2150 50 0001 C CNN
F 3 "~" H 11150 2150 50 0001 C CNN
1 11150 2150
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
Wire Wire Line
11350 2250 11350 2150
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 2150 11300 2150
Text HLabel 10550 2150 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_4_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 2150 11000 2150
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 2250 11350 2250
Text HLabel 10550 2250 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_4_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R19
2021-06-24 15:18:57 +08:00
U 1 1 614E8180
P 10350 2350
F 0 "R19" V 10143 2350 50 0000 C CNN
F 1 "140/1%" V 10234 2350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 2350 50 0001 C CNN
F 3 "~" H 10350 2350 50 0001 C CNN
1 10350 2350
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R20
2021-06-24 15:18:57 +08:00
U 1 1 614E8186
P 10350 2450
F 0 "R20" V 10143 2450 50 0000 C CNN
F 1 "140/1%" V 10234 2450 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 2450 50 0001 C CNN
F 3 "~" H 10350 2450 50 0001 C CNN
1 10350 2450
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R65
2021-06-24 15:18:57 +08:00
U 1 1 614E818C
P 11150 2350
F 0 "R65" V 10943 2350 50 0000 C CNN
F 1 "100/1%" V 11034 2350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 2350 50 0001 C CNN
F 3 "~" H 11150 2350 50 0001 C CNN
1 11150 2350
2021-06-16 17:13:34 +08:00
0 1 1 0
$EndComp
2021-06-24 15:18:57 +08:00
Wire Wire Line
11350 2450 11350 2350
2021-06-24 15:18:57 +08:00
Wire Wire Line
11350 2350 11300 2350
Text HLabel 10550 2350 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_5_N
Wire Wire Line
10500 2350 11000 2350
2021-06-24 15:18:57 +08:00
Wire Wire Line
10500 2450 11350 2450
Text HLabel 10550 2450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_5_P
2021-06-16 17:13:34 +08:00
$Comp
L Device:R R21
2021-06-24 15:18:57 +08:00
U 1 1 614E819A
P 10350 2550
F 0 "R21" V 10143 2550 50 0000 C CNN
F 1 "140/1%" V 10234 2550 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 2550 50 0001 C CNN
F 3 "~" H 10350 2550 50 0001 C CNN
1 10350 2550
2021-06-24 15:18:57 +08:00
0 1 1 0
2021-06-16 17:13:34 +08:00
$EndComp
$Comp
L Device:R R22
2021-06-24 15:18:57 +08:00
U 1 1 614E81A0
P 10350 2650
F 0 "R22" V 10143 2650 50 0000 C CNN
F 1 "140/1%" V 10234 2650 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 2650 50 0001 C CNN
F 3 "~" H 10350 2650 50 0001 C CNN
1 10350 2650
2021-06-24 15:18:57 +08:00
0 1 1 0
2021-06-16 17:13:34 +08:00
$EndComp
$Comp
L Device:R R66
2021-06-24 15:18:57 +08:00
U 1 1 614E81A6
P 11150 2550
F 0 "R66" V 10943 2550 50 0000 C CNN
F 1 "100/1%" V 11034 2550 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 2550 50 0001 C CNN
F 3 "~" H 11150 2550 50 0001 C CNN
1 11150 2550
2021-06-24 15:18:57 +08:00
0 1 1 0
2021-06-16 17:13:34 +08:00
$EndComp
Wire Wire Line
11350 2650 11350 2550
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 2550 11300 2550
Text HLabel 10550 2550 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_6_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 2550 11000 2550
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 2650 11350 2650
Text HLabel 10550 2650 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_6_P
$Comp
L Device:R R23
2021-06-24 15:18:57 +08:00
U 1 1 614E81B2
P 10350 2750
F 0 "R23" V 10143 2750 50 0000 C CNN
F 1 "140/1%" V 10234 2750 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 2750 50 0001 C CNN
F 3 "~" H 10350 2750 50 0001 C CNN
1 10350 2750
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R24
2021-06-24 15:18:57 +08:00
U 1 1 614E81B8
P 10350 2850
F 0 "R24" V 10143 2850 50 0000 C CNN
F 1 "140/1%" V 10234 2850 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 2850 50 0001 C CNN
F 3 "~" H 10350 2850 50 0001 C CNN
1 10350 2850
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R67
2021-06-24 15:18:57 +08:00
U 1 1 614E81BE
P 11150 2750
F 0 "R67" V 10943 2750 50 0000 C CNN
F 1 "100/1%" V 11034 2750 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 2750 50 0001 C CNN
F 3 "~" H 11150 2750 50 0001 C CNN
1 11150 2750
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 2850 11350 2750
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 2750 11300 2750
Text HLabel 10550 2750 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_7_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 2750 11000 2750
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 2850 11350 2850
Text HLabel 10550 2850 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_7_P
$Comp
L Device:R R9
2021-06-24 15:18:57 +08:00
U 1 1 614E81CE
P 10350 1350
F 0 "R9" V 10143 1350 50 0000 C CNN
F 1 "140/1%" V 10234 1350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 1350 50 0001 C CNN
F 3 "~" H 10350 1350 50 0001 C CNN
1 10350 1350
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R10
2021-06-24 15:18:57 +08:00
U 1 1 614E81D4
P 10350 1450
F 0 "R10" V 10143 1450 50 0000 C CNN
F 1 "140/1%" V 10234 1450 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 10280 1450 50 0001 C CNN
F 3 "~" H 10350 1450 50 0001 C CNN
1 10350 1450
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L Device:R R60
2021-06-24 15:18:57 +08:00
U 1 1 614E81DA
P 11150 1350
F 0 "R60" V 10943 1350 50 0000 C CNN
F 1 "100/1%" V 11034 1350 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 11080 1350 50 0001 C CNN
F 3 "~" H 11150 1350 50 0001 C CNN
1 11150 1350
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 1450 11350 1350
2021-06-16 17:13:34 +08:00
Wire Wire Line
11350 1350 11300 1350
Text HLabel 10550 1350 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_0_N
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 1350 11000 1350
2021-06-16 17:13:34 +08:00
Wire Wire Line
10500 1450 11350 1450
Text HLabel 10550 1450 2 50 Input ~ 0
2021-06-24 15:18:57 +08:00
FPGA_EEM0_0_P
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 6350 12850 6350
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 6250 12850 6250
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 4150 12850 4150
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 4050 12850 4050
Text Label 12850 6350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
GNDPLL1
Text Label 12850 4150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
VCCPLL1
Text Label 12850 6250 0 50 ~ 0
2021-06-24 15:18:57 +08:00
GNDPLL0
Text Label 12850 4050 0 50 ~ 0
2021-06-24 15:18:57 +08:00
VCCPLL0
$Comp
L power:+3V3 #PWR032
2021-06-24 15:18:57 +08:00
U 1 1 611127A5
P 12950 3900
F 0 "#PWR032" H 12950 3750 50 0001 C CNN
F 1 "+3V3" V 12965 4028 50 0000 L CNN
F 2 "" H 12950 3900 50 0001 C CNN
F 3 "" H 12950 3900 50 0001 C CNN
1 12950 3900
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L power:+2V5 #PWR031
2021-06-24 15:18:57 +08:00
U 1 1 61110124
P 12950 3400
F 0 "#PWR031" H 12950 3250 50 0001 C CNN
F 1 "+2V5" V 12965 3528 50 0000 L CNN
F 2 "" H 12950 3400 50 0001 C CNN
F 3 "" H 12950 3400 50 0001 C CNN
1 12950 3400
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L power:+3V3 #PWR030
2021-06-24 15:18:57 +08:00
U 1 1 6110BA58
P 12950 2950
F 0 "#PWR030" H 12950 2800 50 0001 C CNN
F 1 "+3V3" V 12965 3078 50 0000 L CNN
F 2 "" H 12950 2950 50 0001 C CNN
F 3 "" H 12950 2950 50 0001 C CNN
1 12950 2950
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L power:+3V3 #PWR029
2021-06-24 15:18:57 +08:00
U 1 1 6110AE73
P 12950 2600
F 0 "#PWR029" H 12950 2450 50 0001 C CNN
F 1 "+3V3" V 12965 2728 50 0000 L CNN
F 2 "" H 12950 2600 50 0001 C CNN
F 3 "" H 12950 2600 50 0001 C CNN
1 12950 2600
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L power:+2V5 #PWR027
2021-06-24 15:18:57 +08:00
U 1 1 6110673B
P 12950 1850
F 0 "#PWR027" H 12950 1700 50 0001 C CNN
F 1 "+2V5" V 12965 1978 50 0000 L CNN
F 2 "" H 12950 1850 50 0001 C CNN
F 3 "" H 12950 1850 50 0001 C CNN
1 12950 1850
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
$Comp
L power:+3V3 #PWR028
2021-06-24 15:18:57 +08:00
U 1 1 610FFF53
P 12950 2150
F 0 "#PWR028" H 12950 2000 50 0001 C CNN
F 1 "+3V3" V 12965 2278 50 0000 L CNN
F 2 "" H 12950 2150 50 0001 C CNN
F 3 "" H 12950 2150 50 0001 C CNN
1 12950 2150
2021-06-24 15:18:57 +08:00
0 1 1 0
$EndComp
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 2250 12850 2350
Connection ~ 12850 2250
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 2250 12850 2250
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 2350 12850 2450
Connection ~ 12850 2350
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 2350 12850 2350
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 2450 12750 2450
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 2150 12850 2250
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 2150 12850 2150
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 2700 12850 2800
Connection ~ 12850 2700
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 2700 12850 2700
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 2800 12750 2800
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 2600 12850 2700
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 2600 12850 2600
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 3050 12850 3150
Connection ~ 12850 3050
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 3050 12850 3050
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 3150 12850 3250
Connection ~ 12850 3150
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 3150 12850 3150
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 3250 12750 3250
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 2950 12850 3050
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 2950 12850 2950
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 3600 12850 3700
Connection ~ 12850 3600
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 3600 12850 3600
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 3500 12850 3600
Connection ~ 12850 3500
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 3500 12850 3500
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 3700 12750 3700
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 3400 12850 3500
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 3400 12850 3400
2021-06-16 17:13:34 +08:00
$Comp
L power:+1V2 #PWR026
2021-06-24 15:18:57 +08:00
U 1 1 61088FD2
P 12950 1150
F 0 "#PWR026" H 12950 1000 50 0001 C CNN
F 1 "+1V2" V 12965 1278 50 0000 L CNN
F 2 "" H 12950 1150 50 0001 C CNN
F 3 "" H 12950 1150 50 0001 C CNN
1 12950 1150
2021-06-24 15:18:57 +08:00
0 1 1 0
2021-06-16 17:13:34 +08:00
$EndComp
$Comp
L power:GND #PWR033
2021-06-24 15:18:57 +08:00
U 1 1 61087D3E
P 12950 4350
F 0 "#PWR033" H 12950 4100 50 0001 C CNN
F 1 "GND" V 12955 4222 50 0000 R CNN
F 2 "" H 12950 4350 50 0001 C CNN
F 3 "" H 12950 4350 50 0001 C CNN
1 12950 4350
2021-06-24 15:18:57 +08:00
0 -1 -1 0
2021-06-16 17:13:34 +08:00
$EndComp
Wire Wire Line
12850 4450 12850 4550
Connection ~ 12850 4450
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 4450 12850 4450
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 4550 12850 4650
Connection ~ 12850 4550
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 4550 12850 4550
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 4650 12850 4750
Connection ~ 12850 4650
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 4650 12850 4650
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 4750 12850 4850
Connection ~ 12850 4750
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 4750 12850 4750
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 4850 12850 4950
Connection ~ 12850 4850
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 4850 12850 4850
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 4950 12850 5050
Connection ~ 12850 4950
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 4950 12850 4950
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 5050 12850 5150
Connection ~ 12850 5050
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 5050 12850 5050
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 5150 12850 5250
Connection ~ 12850 5150
2021-06-16 17:13:34 +08:00
Wire Wire Line
12750 5150 12850 5150
2021-06-16 17:13:34 +08:00
Wire Wire Line
12850 5250 12850 5350
Connection ~ 12850 5250
2021-06-17 17:33:12 +08:00
Wire Wire Line
12750 5250 12850 5250
2021-06-17 17:33:12 +08:00
Wire Wire Line
12850 5350 12850 5450
Connection ~ 12850 5350
2021-06-24 15:18:57 +08:00
Wire Wire Line
12750 5350 12850 5350
2021-06-24 15:18:57 +08:00
Wire Wire Line
12850 5450 12850 5550
Connection ~ 12850 5450
2021-06-24 15:18:57 +08:00
Wire Wire Line
12750 5450 12850 5450
2021-06-24 15:18:57 +08:00
Wire Wire Line
12850 5550 12850 5650
Connection ~ 12850 5550
2021-06-24 15:18:57 +08:00
Wire Wire Line
12750 5550 12850 5550
2021-06-24 15:18:57 +08:00
Wire Wire Line
12850 5650 12850 5750
Connection ~ 12850 5650
2021-06-24 15:18:57 +08:00
Wire Wire Line
12750 5650 12850 5650
2021-06-24 15:18:57 +08:00
Wire Wire Line
12750 5850 12850 5850
2021-06-24 15:18:57 +08:00
Wire Wire Line
12850 5750 12850 5850
Connection ~ 12850 5750
2021-06-18 10:27:05 +08:00
Wire Wire Line
12750 5750 12850 5750
2021-06-18 10:27:05 +08:00
Wire Wire Line
12850 5850 12850 5950
Connection ~ 12850 5850
2021-06-18 10:27:05 +08:00
Wire Wire Line
12850 5950 12850 6050
Connection ~ 12850 5950
2021-06-18 10:27:05 +08:00
Wire Wire Line
12750 5950 12850 5950
2021-06-18 10:27:05 +08:00
Wire Wire Line
12850 6050 12750 6050
2021-06-18 10:27:05 +08:00
Wire Wire Line
12850 4350 12850 4450
2021-06-18 10:27:05 +08:00
Wire Wire Line
12750 4350 12850 4350
2021-06-18 10:27:05 +08:00
Wire Wire Line
12850 1250 12850 1350
Connection ~ 12850 1250
2021-06-18 10:27:05 +08:00
Wire Wire Line
12750 1250 12850 1250
2021-06-24 15:18:57 +08:00
Wire Wire Line
12850 1350 12850 1450
Connection ~ 12850 1350
2021-06-24 15:18:57 +08:00
Wire Wire Line
12750 1350 12850 1350
2021-06-24 15:18:57 +08:00
Wire Wire Line
12850 1450 12850 1550
Connection ~ 12850 1450
2021-06-24 15:18:57 +08:00
Wire Wire Line
12750 1450 12850 1450
2021-06-24 15:18:57 +08:00
Wire Wire Line
12850 1550 12850 1650
Connection ~ 12850 1550
2021-06-24 15:18:57 +08:00
Wire Wire Line
12750 1550 12850 1550
2021-06-24 15:18:57 +08:00
Wire Wire Line
12850 1650 12750 1650
2021-06-24 15:18:57 +08:00
Wire Wire Line
12850 1150 12850 1250
2021-06-24 15:18:57 +08:00
Wire Wire Line
12750 1150 12850 1150
Text Label 10050 1350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_0_P
Text Label 10050 1450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_0_N
Text Label 10050 1550 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_1_P
Text Label 10050 1650 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_1_N
Text Label 10050 1750 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_2_P
Text Label 10050 1850 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_2_N
Text Label 10050 1950 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_3_P
Text Label 10050 2050 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_3_N
Text Label 10050 2150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_4_P
Text Label 10050 2250 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_4_N
Text Label 10050 2350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_5_P
Text Label 10050 2450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_5_N
Text Label 10050 2550 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_6_P
Text Label 10050 2650 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_6_N
Text Label 10050 2750 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_7_P
Text Label 10050 2850 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_7_N
Text Label 10050 3150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_0_P
Text Label 10050 3250 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_0_N
Text Label 10050 3350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_1_P
Text Label 10050 3450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_1_N
Text Label 10050 3550 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_2_P
Text Label 10050 3650 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_2_N
Text Label 10050 3750 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_3_P
Text Label 10050 3850 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_3_N
Text Label 10050 3950 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_4_P
Text Label 10050 4050 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_4_N
Text Label 10050 4150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_5_P
Text Label 10050 4250 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_5_N
Text Label 10050 4350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_6_P
Text Label 10050 4450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_6_N
Text Label 10050 4550 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_7_P
Text Label 10050 4650 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_7_N
Text Label 10050 4950 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_0_P
Text Label 10050 5050 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_0_N
Text Label 10050 5150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_1_P
Text Label 10050 5250 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_1_N
Text Label 10050 5350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_2_P
Text Label 10050 5450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_2_N
Text Label 10050 5550 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_3_P
Text Label 10050 5650 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_3_N
Text Label 10050 5750 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_4_P
Text Label 10050 5850 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_4_N
Text Label 10050 5950 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_5_P
Text Label 10050 6050 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_5_N
Text Label 10050 6150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_6_P
Text Label 10050 6250 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_6_N
Text Label 10050 6350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_7_P
Text Label 10050 6450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_7_N
2021-06-18 10:27:05 +08:00
Wire Wire Line
12750 3900 12950 3900
2021-06-18 10:27:05 +08:00
Wire Wire Line
12950 4350 12850 4350
Connection ~ 12850 4350
2021-06-18 10:27:05 +08:00
Wire Wire Line
12950 3400 12850 3400
Connection ~ 12850 3400
2021-06-18 10:27:05 +08:00
Wire Wire Line
12950 2950 12850 2950
Connection ~ 12850 2950
2021-06-18 10:27:05 +08:00
Wire Wire Line
12950 2600 12850 2600
Connection ~ 12850 2600
2021-06-18 10:27:05 +08:00
Wire Wire Line
12950 2150 12850 2150
Connection ~ 12850 2150
2021-06-18 10:27:05 +08:00
Wire Wire Line
12950 1850 12750 1850
2021-06-18 10:27:05 +08:00
Wire Wire Line
12950 1150 12850 1150
Connection ~ 12850 1150
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 3950 10200 3950
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 4050 10200 4050
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 5150 10200 5150
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 5250 10200 5250
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 5350 10200 5350
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 5450 10200 5450
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 5550 10200 5550
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 5650 10200 5650
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 5750 10200 5750
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 5850 10200 5850
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 5950 10200 5950
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 6050 10200 6050
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 6150 10200 6150
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 6250 10200 6250
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 6350 10200 6350
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 6450 10200 6450
2021-06-18 10:27:05 +08:00
Wire Wire Line
10050 3150 10200 3150
Wire Wire Line
10050 3250 10200 3250
Wire Wire Line
10050 3350 10200 3350
Wire Wire Line
10050 3450 10200 3450
Wire Wire Line
10050 3550 10200 3550
Wire Wire Line
10050 3650 10200 3650
Wire Wire Line
10050 3750 10200 3750
Wire Wire Line
10050 3850 10200 3850
Wire Wire Line
10050 4350 10200 4350
Wire Wire Line
10050 4450 10200 4450
Wire Wire Line
10050 4550 10200 4550
Wire Wire Line
10050 4650 10200 4650
Wire Wire Line
10050 1350 10200 1350
Wire Wire Line
10050 1450 10200 1450
Wire Wire Line
10050 4950 10200 4950
Wire Wire Line
10050 5050 10200 5050
Wire Wire Line
10050 1550 10200 1550
Wire Wire Line
10050 1650 10200 1650
Wire Wire Line
10050 1750 10200 1750
Wire Wire Line
10050 1850 10200 1850
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 1950 10200 1950
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 2050 10200 2050
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 2150 10200 2150
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 2250 10200 2250
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 2350 10200 2350
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 2450 10200 2450
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 2550 10200 2550
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 2650 10200 2650
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 2750 10200 2750
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 2850 10200 2850
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 4150 10200 4150
2021-06-24 15:18:57 +08:00
Wire Wire Line
10050 4250 10200 4250
NoConn ~ 5650 5250
NoConn ~ 5650 5750
NoConn ~ 5650 6050
NoConn ~ 5650 6150
NoConn ~ 5650 6250
NoConn ~ 5650 2050
NoConn ~ 9650 5550
NoConn ~ 9650 5650
NoConn ~ 9650 5750
NoConn ~ 9650 5850
Text Label 9650 6350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_0_N
Text Label 9650 6450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_0_P
Text Label 9650 5350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_1_N
Text Label 9650 5450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_1_P
Text Label 9650 3350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_2_N
Text Label 9650 3450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_2_P
Text Label 9650 4950 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_3_N
Text Label 9650 5050 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_3_P
Text Label 9650 2950 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_4_N
Text Label 9650 3050 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_4_P
Text Label 9650 4550 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_5_N
Text Label 9650 4650 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_5_P
Text Label 9650 2350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_6_N
Text Label 9650 2450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_6_P
Text Label 9650 3550 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_7_N
Text Label 9650 3650 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS0_7_P
Text Label 9650 5950 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_1_N
Text Label 9650 6050 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_1_P
Text Label 9650 5150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_2_N
Text Label 9650 5250 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_2_P
Text Label 9650 4750 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_3_N
Text Label 9650 4850 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_3_P
Text Label 9650 3750 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_7_N
Text Label 9650 3850 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_7_P
Text Label 9650 3150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_0_N
Text Label 9650 3250 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_0_P
Text Label 9650 2550 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_1_N
Text Label 9650 2650 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_1_P
Text Label 9650 1950 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_2_N
Text Label 9650 2050 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_2_P
Text Label 9650 2150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_3_N
Text Label 9650 2250 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_3_P
Text Label 9650 1750 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_4_N
Text Label 9650 1850 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_4_P
Text Label 9650 1550 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_5_N
Text Label 9650 1650 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_5_P
Text Label 9650 2750 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_6_N
Text Label 9650 2850 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_6_P
Text Label 9650 1350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_7_N
Text Label 9650 1450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS2_7_P
Text Label 9650 6150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_0_N
Text Label 9650 6250 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_0_P
Text Label 9650 4050 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_6_P
Text Label 9650 3950 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_6_N
Text Label 9650 4250 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_5_P
Text Label 9650 4150 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_5_N
Text Label 9650 4450 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_4_P
Text Label 9650 4350 0 50 ~ 0
2021-06-24 15:18:57 +08:00
LVDS1_4_N
Text HLabel 7750 2750 2 50 Input ~ 0
FPGA_IO0
Wire Wire Line
7750 2750 7650 2750
Text HLabel 7750 3250 2 50 Input ~ 0
FPGA_IO1
Wire Wire Line
7650 3250 7750 3250
Text HLabel 5750 3050 2 50 Input ~ 0
FPGA_ADC_D0
Wire Wire Line
5750 3050 5650 3050
Text Label 7750 4650 0 50 ~ 0
FPGA_LED
Text Label 7750 5250 0 50 ~ 0
FPGA_KEY
Wire Wire Line
7750 4650 7650 4650
Wire Wire Line
7650 5250 7750 5250
Text Label 13000 7600 0 50 ~ 0
FPGA_KEY
Text Label 13100 7750 0 50 ~ 0
FPGA_LED
Text HLabel 3750 2850 2 50 Input ~ 0
FPGA_FSMC_A2
Wire Wire Line
3750 2850 3700 2850
Text HLabel 3750 3850 2 50 Input ~ 0
FPGA_FSMC_A1
Wire Wire Line
3750 3850 3700 3850
Wire Wire Line
3750 5250 3700 5250
Text HLabel 3750 5250 2 50 Input ~ 0
FPGA_FSMC_D8
Wire Wire Line
3750 2250 3700 2250
Text HLabel 3750 2250 2 50 Input ~ 0
FPGA_FSMC_A7
NoConn ~ 3700 1350
NoConn ~ 3700 1650
NoConn ~ 3700 2150
NoConn ~ 3700 2350
NoConn ~ 3700 3050
NoConn ~ 3700 3250
NoConn ~ 3700 3350
NoConn ~ 3700 3550
NoConn ~ 3700 3750
NoConn ~ 3700 3950
NoConn ~ 3700 4550
NoConn ~ 3700 4650
NoConn ~ 3700 4850
NoConn ~ 3700 5150
NoConn ~ 3700 5450
NoConn ~ 3700 5650
NoConn ~ 3700 5750
NoConn ~ 3700 5950
NoConn ~ 3700 6050
NoConn ~ 3700 6150
NoConn ~ 5650 4750
NoConn ~ 5650 4650
NoConn ~ 5650 4450
NoConn ~ 5650 4350
NoConn ~ 5650 4250
NoConn ~ 5650 4050
NoConn ~ 5650 3850
NoConn ~ 5650 3550
NoConn ~ 5650 3450
NoConn ~ 5650 3350
NoConn ~ 5650 2950
NoConn ~ 5650 2850
NoConn ~ 5650 2650
NoConn ~ 5650 2450
NoConn ~ 5650 2250
NoConn ~ 5650 2150
NoConn ~ 5650 1850
NoConn ~ 5650 1750
NoConn ~ 5650 1650
NoConn ~ 5650 1350
NoConn ~ 5650 1250
NoConn ~ 5650 1150
$Comp
L Device:C C10
U 1 1 611CA559
P 9650 7200
F 0 "C10" V 9398 7200 50 0000 C CNN
F 1 "0.1uF" V 9489 7200 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 9688 7050 50 0001 C CNN
F 3 "~" H 9650 7200 50 0001 C CNN
1 9650 7200
-1 0 0 1
$EndComp
$Comp
L power:GND #PWR013
U 1 1 6120636B
P 3250 10150
F 0 "#PWR013" H 3250 9900 50 0001 C CNN
F 1 "GND" V 3255 10022 50 0000 R CNN
F 2 "" H 3250 10150 50 0001 C CNN
F 3 "" H 3250 10150 50 0001 C CNN
1 3250 10150
1 0 0 -1
$EndComp
Wire Wire Line
3250 10050 3250 10100
Wire Wire Line
3250 9750 3250 9700
$Comp
L power:GND #PWR021
U 1 1 61397A55
P 8750 9450
F 0 "#PWR021" H 8750 9200 50 0001 C CNN
F 1 "GND" V 8755 9322 50 0000 R CNN
F 2 "" H 8750 9450 50 0001 C CNN
F 3 "" H 8750 9450 50 0001 C CNN
1 8750 9450
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR023
U 1 1 613CFCA8
P 8750 10600
F 0 "#PWR023" H 8750 10350 50 0001 C CNN
F 1 "GND" V 8755 10472 50 0000 R CNN
F 2 "" H 8750 10600 50 0001 C CNN
F 3 "" H 8750 10600 50 0001 C CNN
1 8750 10600
1 0 0 -1
$EndComp
Wire Wire Line
3250 9700 3250 9650
NoConn ~ 7650 5450
NoConn ~ 7650 5350
NoConn ~ 7650 5150
NoConn ~ 7650 5050
NoConn ~ 7650 4850
NoConn ~ 7650 4350
NoConn ~ 7650 4250
NoConn ~ 7650 4150
NoConn ~ 7650 3950
NoConn ~ 7650 3850
NoConn ~ 7650 3650
NoConn ~ 7650 3450
NoConn ~ 7650 3350
NoConn ~ 7650 3150
NoConn ~ 7650 3050
NoConn ~ 7650 2950
NoConn ~ 7650 2850
NoConn ~ 7650 2550
NoConn ~ 7650 2450
NoConn ~ 7650 2350
NoConn ~ 7650 2250
NoConn ~ 7650 2150
NoConn ~ 7650 1750
NoConn ~ 7650 1550
NoConn ~ 7650 1350
NoConn ~ 7650 1150
NoConn ~ 12750 1950
$Comp
L power:+2V5 #PWR020
U 1 1 61E6B89D
P 8750 8950
F 0 "#PWR020" H 8750 8800 50 0001 C CNN
F 1 "+2V5" V 8765 9078 50 0000 L CNN
F 2 "" H 8750 8950 50 0001 C CNN
F 3 "" H 8750 8950 50 0001 C CNN
1 8750 8950
1 0 0 -1
$EndComp
$Comp
L power:+3V3 #PWR012
U 1 1 61E6B8A3
P 3250 9650
F 0 "#PWR012" H 3250 9500 50 0001 C CNN
F 1 "+3V3" V 3265 9778 50 0000 L CNN
F 2 "" H 3250 9650 50 0001 C CNN
F 3 "" H 3250 9650 50 0001 C CNN
1 3250 9650
1 0 0 -1
$EndComp
$Comp
L power:+1V2 #PWR022
U 1 1 61E6B8A9
P 8750 10100
F 0 "#PWR022" H 8750 9950 50 0001 C CNN
F 1 "+1V2" V 8765 10228 50 0000 L CNN
F 2 "" H 8750 10100 50 0001 C CNN
F 3 "" H 8750 10100 50 0001 C CNN
1 8750 10100
1 0 0 -1
$EndComp
$Comp
L Device:C C11
U 1 1 62010A4C
P 10050 7200
F 0 "C11" V 9798 7200 50 0000 C CNN
F 1 "0.1uF" V 9889 7200 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 10088 7050 50 0001 C CNN
F 3 "~" H 10050 7200 50 0001 C CNN
1 10050 7200
-1 0 0 1
$EndComp
Wire Wire Line
3650 10050 3650 10100
Wire Wire Line
3650 9750 3650 9700
$Comp
L Device:C C12
U 1 1 6203D958
P 4050 9900
F 0 "C12" V 3798 9900 50 0000 C CNN
F 1 "0.1uF" V 3889 9900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 4088 9750 50 0001 C CNN
F 3 "~" H 4050 9900 50 0001 C CNN
1 4050 9900
-1 0 0 1
$EndComp
Wire Wire Line
4050 10050 4050 10100
Wire Wire Line
4050 9750 4050 9700
$Comp
L Device:C C13
U 1 1 6206AEA7
P 4450 9900
F 0 "C13" V 4198 9900 50 0000 C CNN
F 1 "0.1uF" V 4289 9900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 4488 9750 50 0001 C CNN
F 3 "~" H 4450 9900 50 0001 C CNN
1 4450 9900
-1 0 0 1
$EndComp
Wire Wire Line
4450 10050 4450 10100
Wire Wire Line
4450 9750 4450 9700
$Comp
L Device:C C14
U 1 1 620984B2
P 4850 9900
F 0 "C14" V 4598 9900 50 0000 C CNN
F 1 "0.1uF" V 4689 9900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 4888 9750 50 0001 C CNN
F 3 "~" H 4850 9900 50 0001 C CNN
1 4850 9900
-1 0 0 1
$EndComp
Wire Wire Line
4850 10050 4850 10100
Wire Wire Line
4850 9750 4850 9700
$Comp
L Device:C C15
U 1 1 620C5ACF
P 5250 9900
F 0 "C15" V 4998 9900 50 0000 C CNN
F 1 "0.1uF" V 5089 9900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 5288 9750 50 0001 C CNN
F 3 "~" H 5250 9900 50 0001 C CNN
1 5250 9900
-1 0 0 1
$EndComp
Wire Wire Line
5250 10050 5250 10100
Wire Wire Line
5250 9750 5250 9700
$Comp
L Device:C C16
U 1 1 620F3346
P 5650 9900
F 0 "C16" V 5398 9900 50 0000 C CNN
F 1 "0.1uF" V 5489 9900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 5688 9750 50 0001 C CNN
F 3 "~" H 5650 9900 50 0001 C CNN
1 5650 9900
-1 0 0 1
$EndComp
Wire Wire Line
5650 10050 5650 10100
Wire Wire Line
5650 9750 5650 9700
Wire Wire Line
5650 9700 5250 9700
Connection ~ 3250 9700
Connection ~ 3650 9700
Wire Wire Line
3650 9700 3250 9700
Connection ~ 4050 9700
Wire Wire Line
4050 9700 3650 9700
Connection ~ 4450 9700
Wire Wire Line
4450 9700 4050 9700
Connection ~ 4850 9700
Wire Wire Line
4850 9700 4450 9700
Connection ~ 5250 9700
Wire Wire Line
5250 9700 4850 9700
Wire Wire Line
5650 10100 5250 10100
Connection ~ 3250 10100
Connection ~ 3650 10100
Wire Wire Line
3650 10100 3250 10100
Connection ~ 4050 10100
Wire Wire Line
4050 10100 3650 10100
Connection ~ 4450 10100
Wire Wire Line
4450 10100 4050 10100
Connection ~ 4850 10100
Wire Wire Line
4850 10100 4450 10100
Connection ~ 5250 10100
Wire Wire Line
5250 10100 4850 10100
$Comp
L Device:C C17
U 1 1 62182AD4
P 6050 9900
F 0 "C17" V 5798 9900 50 0000 C CNN
F 1 "0.1nF" V 5889 9900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6088 9750 50 0001 C CNN
F 3 "~" H 6050 9900 50 0001 C CNN
1 6050 9900
-1 0 0 1
$EndComp
Wire Wire Line
6050 10050 6050 10100
Wire Wire Line
6050 9750 6050 9700
$Comp
L Device:C C19
U 1 1 621B31B5
P 9250 7200
F 0 "C19" V 8998 7200 50 0000 C CNN
F 1 "10uF" V 9089 7200 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 9288 7050 50 0001 C CNN
F 3 "~" H 9250 7200 50 0001 C CNN
1 9250 7200
-1 0 0 1
$EndComp
Wire Wire Line
9250 7350 9250 7400
Wire Wire Line
9250 7050 9250 7000
Connection ~ 5650 9700
Wire Wire Line
6050 9700 5650 9700
Connection ~ 5650 10100
Wire Wire Line
6050 10100 5650 10100
$Comp
L Device:C C9
U 1 1 6224994D
P 2850 9900
F 0 "C9" H 2965 9946 50 0000 L CNN
F 1 "10uF" H 2965 9855 50 0000 L CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 2888 9750 50 0001 C CNN
F 3 "~" H 2850 9900 50 0001 C CNN
1 2850 9900
1 0 0 -1
$EndComp
Wire Wire Line
3250 9700 2850 9700
Wire Wire Line
2850 9700 2850 9750
Wire Wire Line
3250 10100 2850 10100
Wire Wire Line
2850 10100 2850 10050
Wire Wire Line
3250 10100 3250 10150
$Comp
L Device:C C27
U 1 1 6249C320
P 8750 9200
F 0 "C27" V 8498 9200 50 0000 C CNN
F 1 "0.1uF" V 8589 9200 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 8788 9050 50 0001 C CNN
F 3 "~" H 8750 9200 50 0001 C CNN
1 8750 9200
-1 0 0 1
$EndComp
Wire Wire Line
8750 9350 8750 9400
Wire Wire Line
8750 9050 8750 9000
Wire Wire Line
8750 9000 8750 8950
$Comp
L Device:C C29
U 1 1 6249C329
P 9150 9200
F 0 "C29" V 8898 9200 50 0000 C CNN
F 1 "0.1uF" V 8989 9200 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 9188 9050 50 0001 C CNN
F 3 "~" H 9150 9200 50 0001 C CNN
1 9150 9200
-1 0 0 1
$EndComp
Wire Wire Line
9150 9350 9150 9400
Wire Wire Line
9150 9050 9150 9000
$Comp
L Device:C C31
U 1 1 6249C331
P 9550 9200
F 0 "C31" V 9298 9200 50 0000 C CNN
F 1 "0.1uF" V 9389 9200 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 9588 9050 50 0001 C CNN
F 3 "~" H 9550 9200 50 0001 C CNN
1 9550 9200
-1 0 0 1
$EndComp
Wire Wire Line
9550 9350 9550 9400
Wire Wire Line
9550 9050 9550 9000
$Comp
L Device:C C33
U 1 1 6249C339
P 9950 9200
F 0 "C33" V 9698 9200 50 0000 C CNN
F 1 "0.1uF" V 9789 9200 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 9988 9050 50 0001 C CNN
F 3 "~" H 9950 9200 50 0001 C CNN
1 9950 9200
-1 0 0 1
$EndComp
Wire Wire Line
9950 9350 9950 9400
Wire Wire Line
9950 9050 9950 9000
$Comp
L Device:C C35
U 1 1 6249C341
P 10350 9200
F 0 "C35" V 10098 9200 50 0000 C CNN
F 1 "0.1uF" V 10189 9200 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 10388 9050 50 0001 C CNN
F 3 "~" H 10350 9200 50 0001 C CNN
1 10350 9200
-1 0 0 1
$EndComp
Wire Wire Line
10350 9350 10350 9400
Wire Wire Line
10350 9050 10350 9000
Connection ~ 8750 9000
Connection ~ 9150 9000
Wire Wire Line
9150 9000 8750 9000
Connection ~ 9550 9000
Wire Wire Line
9550 9000 9150 9000
Connection ~ 9950 9000
Wire Wire Line
9950 9000 9550 9000
Wire Wire Line
10350 9000 9950 9000
Connection ~ 8750 9400
Connection ~ 9150 9400
Wire Wire Line
9150 9400 8750 9400
Connection ~ 9550 9400
Wire Wire Line
9550 9400 9150 9400
Connection ~ 9950 9400
Wire Wire Line
9950 9400 9550 9400
Wire Wire Line
10350 9400 9950 9400
$Comp
L Device:C C25
U 1 1 6249C389
P 8350 9200
F 0 "C25" H 8465 9246 50 0000 L CNN
F 1 "10uF" H 8465 9155 50 0000 L CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 8388 9050 50 0001 C CNN
F 3 "~" H 8350 9200 50 0001 C CNN
1 8350 9200
1 0 0 -1
$EndComp
Wire Wire Line
8750 9000 8350 9000
Wire Wire Line
8350 9000 8350 9050
Wire Wire Line
8750 9400 8350 9400
Wire Wire Line
8350 9400 8350 9350
Wire Wire Line
8750 9400 8750 9450
$Comp
L Device:C C28
U 1 1 6258FF21
P 8750 10350
F 0 "C28" V 8498 10350 50 0000 C CNN
F 1 "0.1uF" V 8589 10350 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 8788 10200 50 0001 C CNN
F 3 "~" H 8750 10350 50 0001 C CNN
1 8750 10350
-1 0 0 1
$EndComp
Wire Wire Line
8750 10500 8750 10550
Wire Wire Line
8750 10200 8750 10150
Wire Wire Line
8750 10150 8750 10100
$Comp
L Device:C C30
U 1 1 6258FF2A
P 9150 10350
F 0 "C30" V 8898 10350 50 0000 C CNN
F 1 "0.1uF" V 8989 10350 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 9188 10200 50 0001 C CNN
F 3 "~" H 9150 10350 50 0001 C CNN
1 9150 10350
-1 0 0 1
$EndComp
Wire Wire Line
9150 10500 9150 10550
Wire Wire Line
9150 10200 9150 10150
$Comp
L Device:C C32
U 1 1 6258FF32
P 9550 10350
F 0 "C32" V 9298 10350 50 0000 C CNN
F 1 "0.1uF" V 9389 10350 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 9588 10200 50 0001 C CNN
F 3 "~" H 9550 10350 50 0001 C CNN
1 9550 10350
-1 0 0 1
$EndComp
Wire Wire Line
9550 10500 9550 10550
Wire Wire Line
9550 10200 9550 10150
$Comp
L Device:C C34
U 1 1 6258FF3A
P 9950 10350
F 0 "C34" V 9698 10350 50 0000 C CNN
F 1 "0.1uF" V 9789 10350 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 9988 10200 50 0001 C CNN
F 3 "~" H 9950 10350 50 0001 C CNN
1 9950 10350
-1 0 0 1
$EndComp
Wire Wire Line
9950 10500 9950 10550
Wire Wire Line
9950 10200 9950 10150
$Comp
L Device:C C36
U 1 1 6258FF42
P 10350 10350
F 0 "C36" V 10098 10350 50 0000 C CNN
F 1 "0.1uF" V 10189 10350 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 10388 10200 50 0001 C CNN
F 3 "~" H 10350 10350 50 0001 C CNN
1 10350 10350
-1 0 0 1
$EndComp
Wire Wire Line
10350 10500 10350 10550
Wire Wire Line
10350 10200 10350 10150
$Comp
L Device:C C37
U 1 1 6258FF4A
P 10750 10350
F 0 "C37" V 10498 10350 50 0000 C CNN
F 1 "0.1uF" V 10589 10350 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 10788 10200 50 0001 C CNN
F 3 "~" H 10750 10350 50 0001 C CNN
1 10750 10350
-1 0 0 1
$EndComp
Wire Wire Line
10750 10500 10750 10550
Wire Wire Line
10750 10200 10750 10150
Connection ~ 8750 10150
Connection ~ 9150 10150
Wire Wire Line
9150 10150 8750 10150
Connection ~ 9550 10150
Wire Wire Line
9550 10150 9150 10150
Connection ~ 9950 10150
Wire Wire Line
9950 10150 9550 10150
Connection ~ 10350 10150
Wire Wire Line
10350 10150 9950 10150
Wire Wire Line
10750 10150 10350 10150
Connection ~ 8750 10550
Connection ~ 9150 10550
Wire Wire Line
9150 10550 8750 10550
Connection ~ 9550 10550
Wire Wire Line
9550 10550 9150 10550
Connection ~ 9950 10550
Wire Wire Line
9950 10550 9550 10550
Connection ~ 10350 10550
Wire Wire Line
10350 10550 9950 10550
Wire Wire Line
10750 10550 10350 10550
$Comp
L Device:C C26
U 1 1 6258FF8A
P 8350 10350
F 0 "C26" H 8465 10396 50 0000 L CNN
F 1 "10uF" H 8465 10305 50 0000 L CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 8388 10200 50 0001 C CNN
F 3 "~" H 8350 10350 50 0001 C CNN
1 8350 10350
1 0 0 -1
$EndComp
Wire Wire Line
8750 10150 8350 10150
Wire Wire Line
8350 10150 8350 10200
Wire Wire Line
8750 10550 8350 10550
Wire Wire Line
8350 10550 8350 10500
Wire Wire Line
8750 10550 8750 10600
NoConn ~ 5650 3650
NoConn ~ 5650 3950
Text Label 5700 4150 0 50 ~ 0
I2C_2_SDA
Text HLabel 5750 4150 2 50 Input ~ 0
FPGA_EEM2_IIC_SDA
Wire Wire Line
5650 4150 5750 4150
Text Label 5700 4550 0 50 ~ 0
I2C_2_SCL
Text HLabel 5750 4550 2 50 Input ~ 0
FPGA_EEM2_IIC_SCL
Wire Wire Line
5650 4550 5750 4550
Wire Wire Line
3700 1850 3750 1850
Text HLabel 3750 1850 2 50 Input ~ 0
FPGA_FSMC_NE1
$Comp
L Device:C C21
U 1 1 61437B16
P 3250 9900
F 0 "C21" V 2998 9900 50 0000 C CNN
F 1 "0.1nF" V 3089 9900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 3288 9750 50 0001 C CNN
F 3 "~" H 3250 9900 50 0001 C CNN
1 3250 9900
-1 0 0 1
$EndComp
Wire Wire Line
9650 7350 9650 7400
Wire Wire Line
9650 7050 9650 7000
$Comp
L Device:C C24
U 1 1 61437B1E
P 3650 9900
F 0 "C24" V 3398 9900 50 0000 C CNN
F 1 "0.1nF" V 3489 9900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 3688 9750 50 0001 C CNN
F 3 "~" H 3650 9900 50 0001 C CNN
1 3650 9900
-1 0 0 1
$EndComp
Wire Wire Line
10050 7350 10050 7400
Wire Wire Line
10050 7050 10050 7000
Wire Wire Line
10050 7000 9650 7000
Connection ~ 9650 7000
Wire Wire Line
9650 7000 9250 7000
Wire Wire Line
10050 7400 9650 7400
Connection ~ 9650 7400
Wire Wire Line
9650 7400 9250 7400
Connection ~ 9250 7000
NoConn ~ 5650 5150
NoConn ~ 5650 5050
NoConn ~ 5650 4950
NoConn ~ 5650 3750
NoConn ~ 5650 5450
$Comp
L Memory_Flash:AT25SF081-SSHD-X U5
U 1 1 6211163A
P 8400 7850
F 0 "U5" H 9044 7896 50 0000 L CNN
F 1 "AT25SF081-SSHD-X" H 9044 7805 50 0000 L CNN
F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 8400 7250 50 0001 C CNN
F 3 "https://www.adestotech.com/wp-content/uploads/DS-AT25SF081_045.pdf" H 8400 7850 50 0001 C CNN
1 8400 7850
1 0 0 -1
$EndComp
Wire Wire Line
8400 6900 8400 7000
Wire Wire Line
8400 7000 9250 7000
Connection ~ 8400 7000
Wire Wire Line
8400 7000 8400 7350
$Comp
L power:GND #PWR0164
U 1 1 6303CA5C
P 10050 7500
F 0 "#PWR0164" H 10050 7250 50 0001 C CNN
F 1 "GND" H 10055 7327 50 0000 C CNN
F 2 "" H 10050 7500 50 0001 C CNN
F 3 "" H 10050 7500 50 0001 C CNN
1 10050 7500
1 0 0 -1
$EndComp
Wire Wire Line
10050 7500 10050 7400
Connection ~ 10050 7400
$Comp
L Device:C C94
U 1 1 630C242B
P 6450 9900
F 0 "C94" V 6198 9900 50 0000 C CNN
F 1 "0.1uF" V 6289 9900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6488 9750 50 0001 C CNN
F 3 "~" H 6450 9900 50 0001 C CNN
1 6450 9900
-1 0 0 1
$EndComp
Wire Wire Line
6450 10050 6450 10100
Wire Wire Line
6450 9750 6450 9700
Wire Wire Line
6450 9700 6050 9700
Wire Wire Line
6450 10100 6050 10100
$Comp
L Device:C C95
U 1 1 630C2435
P 6850 9900
F 0 "C95" V 6598 9900 50 0000 C CNN
F 1 "0.1nF" V 6689 9900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6888 9750 50 0001 C CNN
F 3 "~" H 6850 9900 50 0001 C CNN
1 6850 9900
-1 0 0 1
$EndComp
Wire Wire Line
6850 10050 6850 10100
Wire Wire Line
6850 9750 6850 9700
Connection ~ 6450 9700
Wire Wire Line
6850 9700 6450 9700
Connection ~ 6450 10100
Wire Wire Line
6850 10100 6450 10100
Connection ~ 6050 9700
Connection ~ 6050 10100
$Comp
L Device:C C96
U 1 1 6310DFAE
P 7250 9900
F 0 "C96" V 6998 9900 50 0000 C CNN
F 1 "0.1nF" V 7089 9900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 7288 9750 50 0001 C CNN
F 3 "~" H 7250 9900 50 0001 C CNN
1 7250 9900
-1 0 0 1
$EndComp
Wire Wire Line
7250 10050 7250 10100
Wire Wire Line
7250 9750 7250 9700
Wire Wire Line
7250 9700 6850 9700
Wire Wire Line
7250 10100 6850 10100
Connection ~ 6850 9700
Connection ~ 6850 10100
2021-07-12 10:03:25 +08:00
$Comp
2021-07-12 11:29:03 +08:00
L power:+3V3 #PWR0165
2021-07-12 10:03:25 +08:00
U 1 1 60FE7B32
P 4200 7350
2021-07-12 11:29:03 +08:00
F 0 "#PWR0165" H 4200 7200 50 0001 C CNN
2021-07-12 10:03:25 +08:00
F 1 "+3V3" H 4215 7523 50 0000 C CNN
F 2 "" H 4200 7350 50 0001 C CNN
F 3 "" H 4200 7350 50 0001 C CNN
1 4200 7350
1 0 0 -1
$EndComp
$EndSCHEMATC