2021-06-10 15:16:21 +08:00
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EESchema Schematic File Version 4
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EELAYER 30 0
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EELAYER END
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2021-07-07 16:14:10 +08:00
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$Descr A3 16535 11693
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2021-06-10 15:16:21 +08:00
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encoding utf-8
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2021-06-18 16:13:42 +08:00
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Sheet 3 8
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2021-06-10 15:16:21 +08:00
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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2021-06-16 17:13:34 +08:00
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$Comp
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2021-06-21 17:06:20 +08:00
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L Device:C C8
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2021-06-16 17:13:34 +08:00
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U 1 1 61137BFE
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2021-07-07 16:14:10 +08:00
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P 4250 8100
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F 0 "C8" H 4365 8146 50 0000 L CNN
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F 1 "0.1uF" H 4365 8055 50 0000 L CNN
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F 2 "Capacitor_SMD:C_0402_1005Metric" H 4288 7950 50 0001 C CNN
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F 3 "~" H 4250 8100 50 0001 C CNN
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1 4250 8100
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2021-06-16 17:13:34 +08:00
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1 0 0 -1
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$EndComp
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$Comp
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2021-06-21 17:06:20 +08:00
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L Device:C C9
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2021-06-16 17:13:34 +08:00
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U 1 1 61141436
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2021-07-07 16:14:10 +08:00
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P 4600 8100
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F 0 "C9" H 4715 8146 50 0000 L CNN
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F 1 "10uF" H 4715 8055 50 0000 L CNN
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F 2 "Capacitor_SMD:C_0402_1005Metric" H 4638 7950 50 0001 C CNN
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F 3 "~" H 4600 8100 50 0001 C CNN
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1 4600 8100
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2021-06-16 17:13:34 +08:00
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1 0 0 -1
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$EndComp
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$Comp
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2021-06-24 15:18:57 +08:00
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L Device:R R7
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2021-06-16 17:13:34 +08:00
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U 1 1 61146472
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2021-07-07 16:14:10 +08:00
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P 4250 7650
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F 0 "R7" V 4043 7650 50 0000 C CNN
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F 1 "100" V 4134 7650 50 0000 C CNN
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F 2 "Resistor_SMD:R_0402_1005Metric" V 4180 7650 50 0001 C CNN
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F 3 "~" H 4250 7650 50 0001 C CNN
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1 4250 7650
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2021-06-16 17:13:34 +08:00
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-1 0 0 1
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$EndComp
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$Comp
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2021-06-21 17:06:20 +08:00
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L Device:C C10
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2021-06-16 17:13:34 +08:00
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U 1 1 6117399C
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2021-07-07 16:14:10 +08:00
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P 5000 8100
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F 0 "C10" H 5115 8146 50 0000 L CNN
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F 1 "0.1uF" H 5115 8055 50 0000 L CNN
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F 2 "Capacitor_SMD:C_0402_1005Metric" H 5038 7950 50 0001 C CNN
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F 3 "~" H 5000 8100 50 0001 C CNN
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1 5000 8100
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2021-06-16 17:13:34 +08:00
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1 0 0 -1
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$EndComp
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$Comp
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2021-06-21 17:06:20 +08:00
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L Device:C C11
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2021-06-16 17:13:34 +08:00
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U 1 1 611739A2
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2021-07-07 16:14:10 +08:00
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P 5350 8100
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F 0 "C11" H 5465 8146 50 0000 L CNN
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F 1 "10uF" H 5465 8055 50 0000 L CNN
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F 2 "Capacitor_SMD:C_0402_1005Metric" H 5388 7950 50 0001 C CNN
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F 3 "~" H 5350 8100 50 0001 C CNN
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1 5350 8100
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2021-06-16 17:13:34 +08:00
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1 0 0 -1
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$EndComp
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$Comp
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2021-06-24 15:18:57 +08:00
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L Device:R R10
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2021-06-16 17:13:34 +08:00
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U 1 1 611739A8
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2021-07-07 16:14:10 +08:00
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P 5000 7650
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F 0 "R10" V 4793 7650 50 0000 C CNN
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F 1 "100" V 4884 7650 50 0000 C CNN
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F 2 "Resistor_SMD:R_0402_1005Metric" V 4930 7650 50 0001 C CNN
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F 3 "~" H 5000 7650 50 0001 C CNN
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1 5000 7650
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2021-06-16 17:13:34 +08:00
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-1 0 0 1
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$EndComp
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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5350 7850 5350 7950
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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5000 7850 5350 7850
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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5000 8250 5000 8350
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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5000 8350 5350 8350
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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5350 8350 5350 8250
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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4600 8250 4600 8350
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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4600 8350 4250 8350
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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4250 8350 4250 8250
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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4250 7850 4600 7850
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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4600 7850 4600 7950
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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4250 7850 4250 7950
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2021-06-16 17:13:34 +08:00
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$Comp
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2021-06-24 15:18:57 +08:00
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L power:+1V2 #PWR010
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2021-06-16 17:13:34 +08:00
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U 1 1 61193177
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2021-07-07 16:14:10 +08:00
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P 4250 7400
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F 0 "#PWR010" H 4250 7250 50 0001 C CNN
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F 1 "+1V2" V 4265 7528 50 0000 L CNN
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F 2 "" H 4250 7400 50 0001 C CNN
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F 3 "" H 4250 7400 50 0001 C CNN
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1 4250 7400
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2021-06-16 17:13:34 +08:00
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1 0 0 -1
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$EndComp
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$Comp
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2021-06-22 16:34:02 +08:00
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L power:+1V2 #PWR013
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2021-06-16 17:13:34 +08:00
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U 1 1 61194D75
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2021-07-07 16:14:10 +08:00
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P 5000 7400
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F 0 "#PWR013" H 5000 7250 50 0001 C CNN
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F 1 "+1V2" V 5015 7528 50 0000 L CNN
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F 2 "" H 5000 7400 50 0001 C CNN
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F 3 "" H 5000 7400 50 0001 C CNN
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1 5000 7400
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2021-06-16 17:13:34 +08:00
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1 0 0 -1
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$EndComp
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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5000 7500 5000 7400
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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4250 7500 4250 7400
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Text Label 4650 7850 0 50 ~ 0
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2021-06-16 17:13:34 +08:00
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VCCPLL0
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2021-07-07 16:14:10 +08:00
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Text Label 5400 7850 0 50 ~ 0
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2021-06-16 17:13:34 +08:00
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VCCPLL1
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2021-07-07 16:14:10 +08:00
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Text Label 4650 8350 0 50 ~ 0
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2021-06-16 17:13:34 +08:00
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GNDPLL0
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2021-07-07 16:14:10 +08:00
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Text Label 5400 8350 0 50 ~ 0
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2021-06-16 17:13:34 +08:00
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GNDPLL1
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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4650 7850 4600 7850
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Connection ~ 4600 7850
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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4650 8350 4600 8350
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Connection ~ 4600 8350
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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5400 7850 5350 7850
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Connection ~ 5350 7850
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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5400 8350 5350 8350
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Connection ~ 5350 8350
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2021-06-24 15:18:57 +08:00
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$Comp
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L Power_Protection:PRTR5V0U2X D1
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U 1 1 610B0EF3
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2021-07-07 16:14:10 +08:00
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P 1200 7700
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F 0 "D1" H 1744 7746 50 0000 L CNN
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F 1 "PRTR5V0U2X" H 1744 7655 50 0000 L CNN
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F 2 "Package_TO_SOT_SMD:SOT-143" H 1260 7700 50 0001 C CNN
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F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 1260 7700 50 0001 C CNN
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1 1200 7700
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2021-06-24 15:18:57 +08:00
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1 0 0 -1
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$EndComp
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2021-07-07 16:14:10 +08:00
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Text Label 3800 4600 0 50 ~ 0
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2021-06-24 15:18:57 +08:00
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I2C_0_SDA
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2021-07-07 16:14:10 +08:00
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Text Label 3800 5400 0 50 ~ 0
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2021-06-24 15:18:57 +08:00
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I2C_0_SCL
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2021-07-06 10:28:18 +08:00
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Text Label 3800 5100 0 50 ~ 0
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2021-06-24 15:18:57 +08:00
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I2C_1_SDA
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2021-07-07 16:14:10 +08:00
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Text Label 3800 5700 0 50 ~ 0
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2021-06-24 15:18:57 +08:00
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I2C_1_SCL
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$Comp
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L Power_Protection:PRTR5V0U2X D2
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U 1 1 6137EFAD
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2021-07-07 16:14:10 +08:00
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P 2300 7700
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F 0 "D2" H 2844 7746 50 0000 L CNN
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F 1 "PRTR5V0U2X" H 2844 7655 50 0000 L CNN
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F 2 "Package_TO_SOT_SMD:SOT-143" H 2360 7700 50 0001 C CNN
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F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 2360 7700 50 0001 C CNN
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1 2300 7700
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2021-06-24 15:18:57 +08:00
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1 0 0 -1
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$EndComp
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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5000 7800 5000 7850
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Connection ~ 5000 7850
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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5000 7850 5000 7950
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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4250 7800 4250 7850
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Connection ~ 4250 7850
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2021-06-24 15:18:57 +08:00
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$Comp
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L Power_Protection:PRTR5V0U2X D3
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U 1 1 6150DB5A
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2021-07-07 16:14:10 +08:00
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P 3400 7700
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F 0 "D3" H 3944 7746 50 0000 L CNN
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F 1 "PRTR5V0U2X" H 3944 7655 50 0000 L CNN
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F 2 "Package_TO_SOT_SMD:SOT-143" H 3460 7700 50 0001 C CNN
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F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 3460 7700 50 0001 C CNN
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1 3400 7700
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2021-06-24 15:18:57 +08:00
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1 0 0 -1
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$EndComp
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2021-07-07 16:14:10 +08:00
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Text HLabel 3850 4600 2 50 Input ~ 0
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2021-06-24 15:18:57 +08:00
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FPGA_EEM0_IIC_SDA
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2021-07-07 16:14:10 +08:00
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Text HLabel 3850 5400 2 50 Input ~ 0
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2021-06-24 15:18:57 +08:00
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FPGA_EEM0_IIC_SCL
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2021-07-06 10:28:18 +08:00
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Text HLabel 3850 5100 2 50 Input ~ 0
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2021-06-24 15:18:57 +08:00
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FPGA_EEM1_IIC_SDA
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2021-07-07 16:14:10 +08:00
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Text HLabel 3850 5700 2 50 Input ~ 0
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2021-06-24 15:18:57 +08:00
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FPGA_EEM1_IIC_SCL
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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3750 4600 3850 4600
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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3750 5400 3850 5400
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-06 10:28:18 +08:00
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3750 5100 3850 5100
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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3750 5700 3850 5700
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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1200 7150 1200 7200
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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2300 7200 2300 7150
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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1200 8200 1200 8250
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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3400 8250 3400 8200
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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2300 8200 2300 8250
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Text Label 700 7800 3 50 ~ 0
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2021-06-24 15:18:57 +08:00
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I2C_0_SDA
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2021-07-07 16:14:10 +08:00
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Text Label 1700 7800 3 50 ~ 0
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2021-06-24 15:18:57 +08:00
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I2C_0_SCL
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2021-07-07 16:14:10 +08:00
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Text Label 1800 7800 3 50 ~ 0
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2021-06-24 15:18:57 +08:00
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I2C_1_SDA
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2021-07-07 16:14:10 +08:00
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Text Label 2800 7800 3 50 ~ 0
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2021-06-24 15:18:57 +08:00
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I2C_1_SCL
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2021-07-07 16:14:10 +08:00
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Text Label 2900 7800 3 50 ~ 0
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2021-06-24 15:18:57 +08:00
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I2C_2_SDA
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2021-07-07 16:14:10 +08:00
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Text Label 3900 7800 3 50 ~ 0
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2021-06-24 15:18:57 +08:00
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I2C_2_SCL
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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3900 7800 3900 7700
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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2900 7700 2900 7800
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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2800 7800 2800 7700
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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1800 7800 1800 7700
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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1700 7800 1700 7700
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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700 7800 700 7700
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2021-06-25 16:57:46 +08:00
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Text HLabel 1850 3200 2 50 Input ~ 0
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2021-06-24 15:18:57 +08:00
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FPGA_FSMC_A0
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2021-06-25 16:57:46 +08:00
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Text HLabel 1850 2500 2 50 Input ~ 0
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2021-06-24 15:18:57 +08:00
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|
|
FPGA_FSMC_A3
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 2900 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_A4
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 3400 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_A5
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 4000 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_A6
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 2300 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D0
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 2700 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D1
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 2400 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D2
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 2200 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D3
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 5300 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D4
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 5100 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D5
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 6000 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D6
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 5600 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D7
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 4700 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D9
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 4800 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D10
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 4500 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D11
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 4200 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D12
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 3900 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D13
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 4100 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D14
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 3800 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_D15
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 3200 1800 3200
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 2500 1800 2500
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 2900 1800 2900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 3400 1800 3400
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 4000 1800 4000
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 2300 1800 2300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 2700 1800 2700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 2400 1800 2400
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
1850 2200 1800 2200
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 5300 1800 5300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 5100 1800 5100
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 6000 1800 6000
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 5600 1800 5600
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 4700 1800 4700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 4800 1800 4800
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 4500 1800 4500
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 4200 1800 4200
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 3900 1800 3900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 4100 1800 4100
|
|
|
|
Wire Wire Line
|
|
|
|
1850 3800 1800 3800
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Memory_Flash:AT25SF081-SSHD-X U4
|
|
|
|
U 1 1 6211163A
|
2021-07-07 16:14:10 +08:00
|
|
|
P 6500 7600
|
|
|
|
F 0 "U4" H 7144 7646 50 0000 L CNN
|
|
|
|
F 1 "AT25SF081-SSHD-X" H 7144 7555 50 0000 L CNN
|
|
|
|
F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 6500 7000 50 0001 C CNN
|
|
|
|
F 3 "https://www.adestotech.com/wp-content/uploads/DS-AT25SF081_045.pdf" H 6500 7600 50 0001 C CNN
|
|
|
|
1 6500 7600
|
2021-06-24 15:18:57 +08:00
|
|
|
1 0 0 -1
|
2021-06-16 17:13:34 +08:00
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1200 7150 2300 7150
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
3400 7150 3400 7200
|
|
|
|
Connection ~ 2300 7150
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2300 7150 3400 7150
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
3400 8250 2300 8250
|
|
|
|
Connection ~ 2300 8250
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2300 8250 1200 8250
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L power:GND #PWR09
|
|
|
|
U 1 1 62303F6D
|
2021-07-07 16:14:10 +08:00
|
|
|
P 2300 8300
|
|
|
|
F 0 "#PWR09" H 2300 8050 50 0001 C CNN
|
|
|
|
F 1 "GND" H 2305 8127 50 0000 C CNN
|
|
|
|
F 2 "" H 2300 8300 50 0001 C CNN
|
|
|
|
F 3 "" H 2300 8300 50 0001 C CNN
|
|
|
|
1 2300 8300
|
2021-06-24 15:18:57 +08:00
|
|
|
1 0 0 -1
|
2021-06-16 17:13:34 +08:00
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2300 7100 2300 7150
|
2021-06-24 15:18:57 +08:00
|
|
|
Text HLabel 5800 5300 2 50 Input ~ 0
|
|
|
|
FPGA_CSBSEL0
|
|
|
|
Text HLabel 5800 5400 2 50 Input ~ 0
|
|
|
|
FPGA_CSBSEL1
|
|
|
|
Text HLabel 5800 5900 2 50 Input ~ 0
|
|
|
|
FPGA_SPI_SDO
|
|
|
|
Text HLabel 5800 5800 2 50 Input ~ 0
|
|
|
|
FPGA_SPI_SDI
|
|
|
|
Text HLabel 5800 5600 2 50 Input ~ 0
|
|
|
|
FPGA_SPI_SS
|
|
|
|
Text HLabel 5800 5700 2 50 Input ~ 0
|
|
|
|
FPGA_SPI_SCK
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
5800 5300 5750 5300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
5800 5400 5750 5400
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
5800 5600 5750 5600
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
5800 5700 5750 5700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
5800 5800 5750 5800
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
5800 5900 5750 5900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
5750 6100 5800 6100
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
5750 6200 5800 6200
|
|
|
|
Text HLabel 5800 6100 2 50 Input ~ 0
|
|
|
|
FPGA_CDONE
|
|
|
|
Text HLabel 5800 6200 2 50 Input ~ 0
|
|
|
|
FPGA_CRESET
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
5900 7800 5850 7800
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
5850 7700 5900 7700
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L power:+3V3 #PWR015
|
|
|
|
U 1 1 627E070D
|
2021-07-07 16:14:10 +08:00
|
|
|
P 6500 7050
|
|
|
|
F 0 "#PWR015" H 6500 6900 50 0001 C CNN
|
|
|
|
F 1 "+3V3" H 6515 7223 50 0000 C CNN
|
|
|
|
F 2 "" H 6500 7050 50 0001 C CNN
|
|
|
|
F 3 "" H 6500 7050 50 0001 C CNN
|
|
|
|
1 6500 7050
|
2021-06-24 15:18:57 +08:00
|
|
|
1 0 0 -1
|
2021-06-16 17:13:34 +08:00
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L power:+3V3 #PWR014
|
|
|
|
U 1 1 627E243D
|
2021-07-07 16:14:10 +08:00
|
|
|
P 5850 7900
|
|
|
|
F 0 "#PWR014" H 5850 7750 50 0001 C CNN
|
|
|
|
F 1 "+3V3" H 5865 8073 50 0000 C CNN
|
|
|
|
F 2 "" H 5850 7900 50 0001 C CNN
|
|
|
|
F 3 "" H 5850 7900 50 0001 C CNN
|
|
|
|
1 5850 7900
|
2021-06-24 15:18:57 +08:00
|
|
|
-1 0 0 1
|
2021-06-16 17:13:34 +08:00
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L power:GND #PWR016
|
|
|
|
U 1 1 627E46CA
|
2021-07-07 16:14:10 +08:00
|
|
|
P 6500 8150
|
|
|
|
F 0 "#PWR016" H 6500 7900 50 0001 C CNN
|
|
|
|
F 1 "GND" H 6505 7977 50 0000 C CNN
|
|
|
|
F 2 "" H 6500 8150 50 0001 C CNN
|
|
|
|
F 3 "" H 6500 8150 50 0001 C CNN
|
|
|
|
1 6500 8150
|
2021-06-24 15:18:57 +08:00
|
|
|
1 0 0 -1
|
2021-06-16 17:13:34 +08:00
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6500 8100 6500 8150
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
5850 7700 5850 7800
|
|
|
|
Connection ~ 5850 7800
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
5850 7800 5850 7900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6500 7100 6500 7050
|
2021-06-24 15:18:57 +08:00
|
|
|
Text Label 5750 5700 0 50 ~ 0
|
|
|
|
SPI_SCK
|
|
|
|
Text Label 5750 5600 0 50 ~ 0
|
|
|
|
SPI_SS
|
|
|
|
Text Label 5750 5900 0 50 ~ 0
|
|
|
|
SPI_MOSI
|
|
|
|
Text Label 5750 5800 0 50 ~ 0
|
|
|
|
SPI_MISO
|
2021-07-07 16:14:10 +08:00
|
|
|
Text Label 5850 7500 2 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
SPI_SCK
|
2021-07-07 16:14:10 +08:00
|
|
|
Text Label 5850 7600 2 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
SPI_SS
|
2021-07-07 16:14:10 +08:00
|
|
|
Text Label 5850 7400 2 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
SPI_MOSI
|
2021-07-07 16:14:10 +08:00
|
|
|
Text Label 7150 7400 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
SPI_MISO
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7150 7400 7100 7400
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
5850 7400 5900 7400
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
5850 7500 5900 7500
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
5850 7600 5900 7600
|
2021-06-24 15:18:57 +08:00
|
|
|
Text Label 5750 6100 0 50 ~ 0
|
|
|
|
CDONE
|
|
|
|
Text Label 5750 6200 0 50 ~ 0
|
|
|
|
CRESET
|
2021-07-07 16:14:10 +08:00
|
|
|
Text Label 8550 7750 2 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
SPI_SS
|
2021-07-07 16:14:10 +08:00
|
|
|
Text Label 8550 7650 2 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
CRESET
|
2021-07-07 16:14:10 +08:00
|
|
|
Text Label 8550 7550 2 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
CDONE
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8550 7650 8650 7650
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8650 7750 8550 7750
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8650 7550 8550 7550
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
9150 7650 9050 7650
|
2021-06-24 15:18:57 +08:00
|
|
|
$Comp
|
|
|
|
L power:+3V3 #PWR017
|
|
|
|
U 1 1 62D9CC4C
|
2021-07-07 16:14:10 +08:00
|
|
|
P 9150 7650
|
|
|
|
F 0 "#PWR017" H 9150 7500 50 0001 C CNN
|
|
|
|
F 1 "+3V3" V 9165 7778 50 0000 L CNN
|
|
|
|
F 2 "" H 9150 7650 50 0001 C CNN
|
|
|
|
F 3 "" H 9150 7650 50 0001 C CNN
|
|
|
|
1 9150 7650
|
2021-06-24 15:18:57 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
9050 7650 9050 7750
|
|
|
|
Connection ~ 9050 7650
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8950 7650 9050 7650
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
9050 7750 8950 7750
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
9050 7550 9050 7650
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8950 7550 9050 7550
|
2021-06-24 15:18:57 +08:00
|
|
|
$Comp
|
|
|
|
L Device:R R61
|
|
|
|
U 1 1 62CE70DD
|
2021-07-07 16:14:10 +08:00
|
|
|
P 8800 7750
|
|
|
|
F 0 "R61" V 8800 7900 50 0000 C CNN
|
|
|
|
F 1 "10k" V 8800 7750 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8730 7750 50 0001 C CNN
|
|
|
|
F 3 "~" H 8800 7750 50 0001 C CNN
|
|
|
|
1 8800 7750
|
2021-06-24 15:18:57 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:R R60
|
|
|
|
U 1 1 62CBFB4D
|
2021-07-07 16:14:10 +08:00
|
|
|
P 8800 7650
|
|
|
|
F 0 "R60" V 8800 7800 50 0000 C CNN
|
|
|
|
F 1 "10k" V 8800 7650 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8730 7650 50 0001 C CNN
|
|
|
|
F 3 "~" H 8800 7650 50 0001 C CNN
|
|
|
|
1 8800 7650
|
2021-06-24 15:18:57 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:R R59
|
|
|
|
U 1 1 62C9E4F5
|
2021-07-07 16:14:10 +08:00
|
|
|
P 8800 7550
|
|
|
|
F 0 "R59" V 8800 7700 50 0000 C CNN
|
|
|
|
F 1 "10k" V 8800 7550 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8730 7550 50 0001 C CNN
|
|
|
|
F 3 "~" H 8800 7550 50 0001 C CNN
|
|
|
|
1 8800 7550
|
2021-06-24 15:18:57 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
2021-06-25 18:15:56 +08:00
|
|
|
Text HLabel 3850 5600 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IIC_SDA
|
2021-06-25 18:15:56 +08:00
|
|
|
Text HLabel 3850 5300 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IIC_SCL
|
|
|
|
Wire Wire Line
|
2021-06-25 18:15:56 +08:00
|
|
|
3750 5600 3850 5600
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 18:15:56 +08:00
|
|
|
3750 5300 3850 5300
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 3850 3000 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_ADC_D1
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 3850 2900 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_ADC_D2
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 3850 2500 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_ADC_D3
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 3850 2100 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_ADC_D4
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 3850 2300 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_ADC_D5
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 3850 1700 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_ADC_D6
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 3850 1300 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_ADC_D7
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 3850 1200 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_ADC_CLK
|
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
3850 3000 3750 3000
|
|
|
|
Wire Wire Line
|
|
|
|
3850 2900 3750 2900
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
3850 2500 3750 2500
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
|
|
|
3850 2100 3750 2100
|
|
|
|
Wire Wire Line
|
|
|
|
3850 2300 3750 2300
|
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
3850 1700 3750 1700
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
3850 1300 3750 1300
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
3850 1200 3750 1200
|
|
|
|
Text HLabel 1850 1700 2 50 Input ~ 0
|
2021-07-07 16:14:10 +08:00
|
|
|
FPGA_FSMC_NWE
|
|
|
|
Text HLabel 1850 1200 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_NOE
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 1500 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_NBL0
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 1300 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_NBL1
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 900 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_NL
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 1850 1800 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_CLK
|
2021-07-07 16:14:10 +08:00
|
|
|
Text HLabel 1850 1000 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_FSMC_NWAIT
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1850 1700 1800 1700
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1800 1200 1850 1200
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 1500 1800 1500
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1800 1300 1850 1300
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1850 900 1800 900
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
1800 1800 1850 1800
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1850 1000 1800 1000
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 2400 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO2
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 3500 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO3
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 1700 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO4
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 3300 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO5
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 1800 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO6
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 3800 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO7
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 1600 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO8
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 4200 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO9
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 1400 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO10
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 4300 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO11
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 1200 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO12
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 4700 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO13
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 1000 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO14
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 4500 2 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
FPGA_IO15
|
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5850 2400 5750 2400
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5750 3500 5850 3500
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5850 1700 5750 1700
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5850 3300 5750 3300
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5850 1800 5750 1800
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5850 3800 5750 3800
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5850 1600 5750 1600
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5850 4200 5750 4200
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5850 1400 5750 1400
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5850 4300 5750 4300
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5850 1200 5750 1200
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5850 4700 5750 4700
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5750 1000 5850 1000
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-06-25 16:57:46 +08:00
|
|
|
5750 4500 5850 4500
|
2021-07-07 16:14:10 +08:00
|
|
|
Text GLabel 2300 7100 1 50 Input ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
+3V3MP
|
|
|
|
$Comp
|
|
|
|
L TestAutomation:ICE40HX8K-CT256 U3
|
|
|
|
U 1 1 623CB106
|
|
|
|
P 1100 3500
|
|
|
|
F 0 "U3" H 1207 6469 50 0000 C CNN
|
|
|
|
F 1 "ICE40HX8K-CT256" H 1207 6378 50 0000 C CNN
|
|
|
|
F 2 "TestAutomation:iCE40-BGA256C80P16X16_1400X1400X170" V 800 2800 50 0001 L BNN
|
|
|
|
F 3 "" H 1100 3500 50 0001 L BNN
|
|
|
|
F 4 "3.4" V 1000 3400 50 0001 L BNN "PART_REV"
|
|
|
|
F 5 "IPC-7351B" V 900 3250 50 0001 L BNN "STANDARD"
|
|
|
|
F 6 "Lattice Semiconductor" V 1100 3100 50 0001 L BNN "MANUFACTURER"
|
|
|
|
1 1100 3500
|
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L TestAutomation:ICE40HX8K-CT256 U3
|
|
|
|
U 2 1 6253F35F
|
|
|
|
P 3050 3500
|
|
|
|
F 0 "U3" H 3157 6480 50 0000 C CNN
|
|
|
|
F 1 "ICE40HX8K-CT256" H 3157 6389 50 0000 C CNN
|
|
|
|
F 2 "TestAutomation:iCE40-BGA256C80P16X16_1400X1400X170" V 2750 2800 50 0001 L BNN
|
|
|
|
F 3 "" H 3050 3500 50 0001 L BNN
|
|
|
|
F 4 "3.4" V 2950 3400 50 0001 L BNN "PART_REV"
|
|
|
|
F 5 "IPC-7351B" V 2850 3250 50 0001 L BNN "STANDARD"
|
|
|
|
F 6 "Lattice Semiconductor" V 3050 3100 50 0001 L BNN "MANUFACTURER"
|
|
|
|
2 3050 3500
|
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L TestAutomation:ICE40HX8K-CT256 U3
|
|
|
|
U 3 1 62546FE8
|
|
|
|
P 5050 3500
|
|
|
|
F 0 "U3" H 5157 6470 50 0000 C CNN
|
|
|
|
F 1 "ICE40HX8K-CT256" H 5157 6379 50 0000 C CNN
|
|
|
|
F 2 "TestAutomation:iCE40-BGA256C80P16X16_1400X1400X170" V 4750 2800 50 0001 L BNN
|
|
|
|
F 3 "" H 5050 3500 50 0001 L BNN
|
|
|
|
F 4 "3.4" V 4950 3400 50 0001 L BNN "PART_REV"
|
|
|
|
F 5 "IPC-7351B" V 4850 3250 50 0001 L BNN "STANDARD"
|
|
|
|
F 6 "Lattice Semiconductor" V 5050 3100 50 0001 L BNN "MANUFACTURER"
|
|
|
|
3 5050 3500
|
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L TestAutomation:ICE40HX8K-CT256 U3
|
|
|
|
U 4 1 62557659
|
|
|
|
P 7050 3700
|
|
|
|
F 0 "U3" H 7157 6668 50 0000 C CNN
|
|
|
|
F 1 "ICE40HX8K-CT256" H 7157 6577 50 0000 C CNN
|
|
|
|
F 2 "TestAutomation:iCE40-BGA256C80P16X16_1400X1400X170" V 6750 3000 50 0001 L BNN
|
|
|
|
F 3 "" H 7050 3700 50 0001 L BNN
|
|
|
|
F 4 "3.4" V 6950 3600 50 0001 L BNN "PART_REV"
|
|
|
|
F 5 "IPC-7351B" V 6850 3450 50 0001 L BNN "STANDARD"
|
|
|
|
F 6 "Lattice Semiconductor" V 7050 3300 50 0001 L BNN "MANUFACTURER"
|
|
|
|
4 7050 3700
|
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:Q_NPN_BEC Q?
|
|
|
|
U 1 1 61C9A1CC
|
2021-07-07 16:14:10 +08:00
|
|
|
P 10100 7700
|
2021-06-24 15:18:57 +08:00
|
|
|
AR Path="/60E3407A/61C9A1CC" Ref="Q?" Part="1"
|
|
|
|
AR Path="/60C0E996/61C9A1CC" Ref="Q1" Part="1"
|
2021-07-07 16:14:10 +08:00
|
|
|
F 0 "Q1" H 10290 7746 50 0000 L CNN
|
|
|
|
F 1 "PMBT3904" H 10290 7655 50 0000 L CNN
|
|
|
|
F 2 "Package_TO_SOT_SMD:SOT-23" H 10300 7800 50 0001 C CNN
|
|
|
|
F 3 "~" H 10100 7700 50 0001 C CNN
|
|
|
|
1 10100 7700
|
2021-06-25 18:15:56 +08:00
|
|
|
0 1 1 0
|
2021-06-24 15:18:57 +08:00
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
10400 7500 11200 7500
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
10200 7500 10100 7500
|
2021-06-24 15:18:57 +08:00
|
|
|
$Comp
|
|
|
|
L Device:R_Small R6
|
|
|
|
U 1 1 623C0DC2
|
2021-07-07 16:14:10 +08:00
|
|
|
P 10300 7500
|
|
|
|
F 0 "R6" H 10359 7546 50 0000 L CNN
|
|
|
|
F 1 "10k" H 10359 7455 50 0000 L CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" H 10300 7500 50 0001 C CNN
|
|
|
|
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1 10800 7800
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L Device:LED D4
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1 10500 7800
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$EndComp
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L power:+3V3 #PWR011
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P 11050 7800
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F 3 "" H 11050 7800 50 0001 C CNN
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1 11050 7800
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$EndComp
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L power:GND #PWR012
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P 9750 7800
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F 0 "#PWR012" H 9750 7550 50 0001 C CNN
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F 3 "" H 9750 7800 50 0001 C CNN
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1 9750 7800
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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10900 7800 10950 7800
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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10700 7800 10650 7800
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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10350 7800 10300 7800
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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9900 7800 9800 7800
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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9800 7800 9750 7800
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Connection ~ 9800 7800
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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9800 7350 9800 7800
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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2300 8250 2300 8300
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2021-06-24 15:18:57 +08:00
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$Comp
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L Switch:SW_Push SW?
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AR Path="/60C2FDBB/6100CA18" Ref="SW?" Part="1"
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AR Path="/60C0E996/6100CA18" Ref="SW1" Part="1"
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2021-07-07 16:14:10 +08:00
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F 3 "~" H 10400 7550 50 0001 C CNN
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1 10400 7350
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1 0 0 -1
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2021-06-24 15:18:57 +08:00
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$EndComp
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$Comp
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L Device:R_Small R8
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2021-07-07 16:14:10 +08:00
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P 10800 7700
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F 2 "Resistor_SMD:R_0402_1005Metric" H 10800 7700 50 0001 C CNN
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|
F 3 "~" H 10800 7700 50 0001 C CNN
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1 10800 7700
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0 -1 -1 0
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$EndComp
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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11100 7350 10650 7350
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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10900 7700 10950 7700
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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10950 7700 10950 7800
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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10950 7800 11050 7800
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Connection ~ 10950 7800
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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10700 7700 10650 7700
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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10650 7700 10650 7350
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Connection ~ 10650 7350
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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10650 7350 10600 7350
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2021-06-24 15:18:57 +08:00
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Wire Wire Line
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2021-07-07 16:14:10 +08:00
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10200 7350 9800 7350
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2021-06-24 15:18:57 +08:00
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$Comp
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L TestAutomation:ICE40HX8K-CT256 U3
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U 5 1 6256A27C
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P 10150 3550
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5 10150 3550
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1 0 0 -1
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$EndComp
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$Comp
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L Device:R R45
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P 8450 4900
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AR Path="/60C0E996/60DF7E88" Ref="R45" Part="1"
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AR Path="/60C2FDBB/60DF7E88" Ref="R?" Part="1"
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F 0 "R45" V 8243 4900 50 0000 C CNN
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F 1 "140/1%" V 8334 4900 50 0000 C CNN
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2021-06-30 14:59:13 +08:00
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F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 4900 50 0001 C CNN
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2021-06-24 15:18:57 +08:00
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F 3 "~" H 8450 4900 50 0001 C CNN
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1 8450 4900
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$EndComp
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$Comp
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L Device:R R46
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U 1 1 60DF7E82
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P 8450 5000
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AR Path="/60C0E996/60DF7E82" Ref="R46" Part="1"
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AR Path="/60C2FDBB/60DF7E82" Ref="R?" Part="1"
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F 0 "R46" V 8243 5000 50 0000 C CNN
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|
F 1 "140/1%" V 8334 5000 50 0000 C CNN
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2021-06-30 14:59:13 +08:00
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F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 5000 50 0001 C CNN
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2021-06-24 15:18:57 +08:00
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F 3 "~" H 8450 5000 50 0001 C CNN
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1 8450 5000
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0 1 1 0
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$EndComp
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$Comp
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L Device:R R79
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U 1 1 60DF7E7C
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P 9250 4900
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AR Path="/60C0E996/60DF7E7C" Ref="R79" Part="1"
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AR Path="/60C2FDBB/60DF7E7C" Ref="R?" Part="1"
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F 0 "R79" V 9043 4900 50 0000 C CNN
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F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 4900 50 0001 C CNN
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F 3 "~" H 9250 4900 50 0001 C CNN
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1 9250 4900
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0 1 1 0
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$EndComp
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Wire Wire Line
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9450 5000 9450 4900
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Wire Wire Line
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Text HLabel 8650 4900 2 50 Input ~ 0
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FPGA_EEM2_1_N
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Wire Wire Line
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8600 4900 9100 4900
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Wire Wire Line
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8600 5000 9450 5000
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Text HLabel 8650 5000 2 50 Input ~ 0
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FPGA_EEM2_1_P
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$Comp
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L Device:R R47
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U 1 1 60DF7E6E
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P 8450 5100
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AR Path="/60C0E996/60DF7E6E" Ref="R47" Part="1"
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|
AR Path="/60C2FDBB/60DF7E6E" Ref="R?" Part="1"
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F 0 "R47" V 8243 5100 50 0000 C CNN
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F 1 "140/1%" V 8334 5100 50 0000 C CNN
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2021-06-30 14:59:13 +08:00
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|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 5100 50 0001 C CNN
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2021-06-24 15:18:57 +08:00
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F 3 "~" H 8450 5100 50 0001 C CNN
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1 8450 5100
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0 1 1 0
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$EndComp
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$Comp
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L Device:R R48
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U 1 1 60DF7E68
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P 8450 5200
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|
AR Path="/60C0E996/60DF7E68" Ref="R48" Part="1"
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|
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|
AR Path="/60C2FDBB/60DF7E68" Ref="R?" Part="1"
|
|
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|
F 0 "R48" V 8243 5200 50 0000 C CNN
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|
F 1 "140/1%" V 8334 5200 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 5200 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 5200 50 0001 C CNN
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|
1 8450 5200
|
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0 1 1 0
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$EndComp
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$Comp
|
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L Device:R R80
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|
U 1 1 60DF7E62
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|
|
|
P 9250 5100
|
|
|
|
AR Path="/60C0E996/60DF7E62" Ref="R80" Part="1"
|
|
|
|
AR Path="/60C2FDBB/60DF7E62" Ref="R?" Part="1"
|
|
|
|
F 0 "R80" V 9043 5100 50 0000 C CNN
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|
F 1 "100/1%" V 9134 5100 50 0000 C CNN
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|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 5100 50 0001 C CNN
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|
F 3 "~" H 9250 5100 50 0001 C CNN
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1 9250 5100
|
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0 1 1 0
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$EndComp
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Wire Wire Line
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9450 5200 9450 5100
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Wire Wire Line
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9450 5100 9400 5100
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Text HLabel 8650 5100 2 50 Input ~ 0
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FPGA_EEM2_2_N
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Wire Wire Line
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8600 5100 9100 5100
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Wire Wire Line
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8600 5200 9450 5200
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Text HLabel 8650 5200 2 50 Input ~ 0
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FPGA_EEM2_2_P
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$Comp
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L Device:R R49
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U 1 1 60DF7E56
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P 8450 5300
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|
AR Path="/60C0E996/60DF7E56" Ref="R49" Part="1"
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|
AR Path="/60C2FDBB/60DF7E56" Ref="R?" Part="1"
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|
F 0 "R49" V 8243 5300 50 0000 C CNN
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|
F 1 "140/1%" V 8334 5300 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 5300 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 5300 50 0001 C CNN
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|
1 8450 5300
|
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0 1 1 0
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$EndComp
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$Comp
|
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L Device:R R50
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|
U 1 1 60DF7E50
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P 8450 5400
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|
|
AR Path="/60C0E996/60DF7E50" Ref="R50" Part="1"
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|
|
|
AR Path="/60C2FDBB/60DF7E50" Ref="R?" Part="1"
|
|
|
|
F 0 "R50" V 8243 5400 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 5400 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 5400 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 5400 50 0001 C CNN
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|
1 8450 5400
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0 1 1 0
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$EndComp
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$Comp
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L Device:R R81
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|
U 1 1 60DF7E4A
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|
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P 9250 5300
|
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|
|
AR Path="/60C0E996/60DF7E4A" Ref="R81" Part="1"
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|
|
|
AR Path="/60C2FDBB/60DF7E4A" Ref="R?" Part="1"
|
|
|
|
F 0 "R81" V 9043 5300 50 0000 C CNN
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|
|
|
F 1 "100/1%" V 9134 5300 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 5300 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 5300 50 0001 C CNN
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|
1 9250 5300
|
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0 1 1 0
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$EndComp
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Wire Wire Line
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9450 5400 9450 5300
|
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|
Wire Wire Line
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|
9450 5300 9400 5300
|
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|
Text HLabel 8650 5300 2 50 Input ~ 0
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|
|
FPGA_EEM2_3_N
|
|
|
|
Wire Wire Line
|
|
|
|
8600 5300 9100 5300
|
|
|
|
Wire Wire Line
|
|
|
|
8600 5400 9450 5400
|
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|
|
Text HLabel 8650 5400 2 50 Input ~ 0
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FPGA_EEM2_3_P
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$Comp
|
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L Device:R R51
|
|
|
|
U 1 1 60DF7E3A
|
|
|
|
P 8450 5500
|
|
|
|
AR Path="/60C0E996/60DF7E3A" Ref="R51" Part="1"
|
|
|
|
AR Path="/60C2FDBB/60DF7E3A" Ref="R?" Part="1"
|
|
|
|
F 0 "R51" V 8243 5500 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 5500 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 5500 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 5500 50 0001 C CNN
|
|
|
|
1 8450 5500
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R52
|
|
|
|
U 1 1 60DF7E34
|
|
|
|
P 8450 5600
|
|
|
|
AR Path="/60C0E996/60DF7E34" Ref="R52" Part="1"
|
|
|
|
AR Path="/60C2FDBB/60DF7E34" Ref="R?" Part="1"
|
|
|
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|
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|
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Wire Wire Line
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8600 5500 9100 5500
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FPGA_EEM2_4_P
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|
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F 3 "~" H 8450 5700 50 0001 C CNN
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AR Path="/60C0E996/60DF7E1A" Ref="R54" Part="1"
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|
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F 0 "R54" V 8243 5800 50 0000 C CNN
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|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 5800 50 0001 C CNN
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|
|
F 3 "~" H 8450 5800 50 0001 C CNN
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|
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P 9250 5700
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AR Path="/60C0E996/60DF7E14" Ref="R83" Part="1"
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|
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AR Path="/60C2FDBB/60DF7E14" Ref="R?" Part="1"
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F 0 "R83" V 9043 5700 50 0000 C CNN
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F 3 "~" H 9250 5700 50 0001 C CNN
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Wire Wire Line
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2021-06-24 15:18:57 +08:00
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9450 5800 9450 5700
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2021-06-16 17:13:34 +08:00
|
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Wire Wire Line
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Text HLabel 8650 5700 2 50 Input ~ 0
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FPGA_EEM2_5_N
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2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-06-24 15:18:57 +08:00
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|
8600 5700 9100 5700
|
2021-06-16 17:13:34 +08:00
|
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Wire Wire Line
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2021-06-24 15:18:57 +08:00
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8600 5800 9450 5800
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Text HLabel 8650 5800 2 50 Input ~ 0
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FPGA_EEM2_5_P
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$Comp
|
2021-06-24 15:18:57 +08:00
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|
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L Device:R R55
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|
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|
|
|
P 8450 5900
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|
|
AR Path="/60C0E996/60DF7E06" Ref="R55" Part="1"
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|
|
|
AR Path="/60C2FDBB/60DF7E06" Ref="R?" Part="1"
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|
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|
F 0 "R55" V 8243 5900 50 0000 C CNN
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|
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|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 5900 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 5900 50 0001 C CNN
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1 8450 5900
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0 1 1 0
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$Comp
|
2021-06-24 15:18:57 +08:00
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|
U 1 1 60DF7E00
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|
|
|
P 8450 6000
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|
|
AR Path="/60C0E996/60DF7E00" Ref="R56" Part="1"
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|
|
|
AR Path="/60C2FDBB/60DF7E00" Ref="R?" Part="1"
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|
F 0 "R56" V 8243 6000 50 0000 C CNN
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|
F 1 "140/1%" V 8334 6000 50 0000 C CNN
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2021-06-30 14:59:13 +08:00
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|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 6000 50 0001 C CNN
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2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 6000 50 0001 C CNN
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1 8450 6000
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0 1 1 0
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$Comp
|
2021-06-24 15:18:57 +08:00
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|
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L Device:R R84
|
|
|
|
U 1 1 60DF7DFA
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|
|
|
P 9250 5900
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|
|
|
AR Path="/60C0E996/60DF7DFA" Ref="R84" Part="1"
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|
|
|
AR Path="/60C2FDBB/60DF7DFA" Ref="R?" Part="1"
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|
|
|
F 0 "R84" V 9043 5900 50 0000 C CNN
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|
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|
F 1 "100/1%" V 9134 5900 50 0000 C CNN
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|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 5900 50 0001 C CNN
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|
|
|
F 3 "~" H 9250 5900 50 0001 C CNN
|
|
|
|
1 9250 5900
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2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
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$EndComp
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Wire Wire Line
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2021-06-24 15:18:57 +08:00
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|
|
9450 6000 9450 5900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
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2021-06-24 15:18:57 +08:00
|
|
|
9450 5900 9400 5900
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|
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|
Text HLabel 8650 5900 2 50 Input ~ 0
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FPGA_EEM2_6_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 5900 9100 5900
|
2021-06-16 17:13:34 +08:00
|
|
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Wire Wire Line
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2021-06-24 15:18:57 +08:00
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8600 6000 9450 6000
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Text HLabel 8650 6000 2 50 Input ~ 0
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FPGA_EEM2_6_P
|
|
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$Comp
|
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L Device:R R57
|
|
|
|
U 1 1 60DF7DEE
|
|
|
|
P 8450 6100
|
|
|
|
AR Path="/60C0E996/60DF7DEE" Ref="R57" Part="1"
|
|
|
|
AR Path="/60C2FDBB/60DF7DEE" Ref="R?" Part="1"
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|
|
F 0 "R57" V 8243 6100 50 0000 C CNN
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|
F 1 "140/1%" V 8334 6100 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 6100 50 0001 C CNN
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2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 6100 50 0001 C CNN
|
|
|
|
1 8450 6100
|
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|
0 1 1 0
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$EndComp
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$Comp
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L Device:R R58
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|
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|
U 1 1 60DF7DE8
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|
|
|
P 8450 6200
|
|
|
|
AR Path="/60C0E996/60DF7DE8" Ref="R58" Part="1"
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|
|
|
AR Path="/60C2FDBB/60DF7DE8" Ref="R?" Part="1"
|
|
|
|
F 0 "R58" V 8243 6200 50 0000 C CNN
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|
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|
F 1 "140/1%" V 8334 6200 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 6200 50 0001 C CNN
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2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 6200 50 0001 C CNN
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|
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|
1 8450 6200
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0 1 1 0
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$EndComp
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$Comp
|
|
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L Device:R R85
|
|
|
|
U 1 1 60DF7DE2
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|
|
|
P 9250 6100
|
|
|
|
AR Path="/60C0E996/60DF7DE2" Ref="R85" Part="1"
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|
|
|
AR Path="/60C2FDBB/60DF7DE2" Ref="R?" Part="1"
|
|
|
|
F 0 "R85" V 9043 6100 50 0000 C CNN
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|
|
|
F 1 "100/1%" V 9134 6100 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 6100 50 0001 C CNN
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|
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|
F 3 "~" H 9250 6100 50 0001 C CNN
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|
1 9250 6100
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0 1 1 0
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$EndComp
|
2021-06-16 17:13:34 +08:00
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Wire Wire Line
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2021-06-24 15:18:57 +08:00
|
|
|
9450 6200 9450 6100
|
2021-06-16 17:13:34 +08:00
|
|
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Wire Wire Line
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2021-06-24 15:18:57 +08:00
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|
|
9450 6100 9400 6100
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Text HLabel 8650 6100 2 50 Input ~ 0
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FPGA_EEM2_7_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
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2021-06-24 15:18:57 +08:00
|
|
|
8600 6100 9100 6100
|
2021-06-16 17:13:34 +08:00
|
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Wire Wire Line
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2021-06-24 15:18:57 +08:00
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8600 6200 9450 6200
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Text HLabel 8650 6200 2 50 Input ~ 0
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FPGA_EEM2_7_P
|
2021-06-16 17:13:34 +08:00
|
|
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$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R43
|
|
|
|
U 1 1 60DF7DD2
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|
|
|
P 8450 4700
|
|
|
|
AR Path="/60C0E996/60DF7DD2" Ref="R43" Part="1"
|
|
|
|
AR Path="/60C2FDBB/60DF7DD2" Ref="R?" Part="1"
|
|
|
|
F 0 "R43" V 8243 4700 50 0000 C CNN
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|
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|
F 1 "140/1%" V 8334 4700 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 4700 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 4700 50 0001 C CNN
|
|
|
|
1 8450 4700
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
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|
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$EndComp
|
|
|
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$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R44
|
|
|
|
U 1 1 60DF7DCC
|
|
|
|
P 8450 4800
|
|
|
|
AR Path="/60C0E996/60DF7DCC" Ref="R44" Part="1"
|
|
|
|
AR Path="/60C2FDBB/60DF7DCC" Ref="R?" Part="1"
|
|
|
|
F 0 "R44" V 8243 4800 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 4800 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 4800 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 4800 50 0001 C CNN
|
|
|
|
1 8450 4800
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R78
|
|
|
|
U 1 1 60DF7DC6
|
|
|
|
P 9250 4700
|
|
|
|
AR Path="/60C0E996/60DF7DC6" Ref="R78" Part="1"
|
|
|
|
AR Path="/60C2FDBB/60DF7DC6" Ref="R?" Part="1"
|
|
|
|
F 0 "R78" V 9043 4700 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 4700 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 4700 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 4700 50 0001 C CNN
|
|
|
|
1 9250 4700
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
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|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 4800 9450 4700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 4700 9400 4700
|
|
|
|
Text HLabel 8650 4700 2 50 Input ~ 0
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|
|
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FPGA_EEM2_0_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 4700 9100 4700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 4800 9450 4800
|
|
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Text HLabel 8650 4800 2 50 Input ~ 0
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FPGA_EEM2_0_P
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R29
|
|
|
|
U 1 1 60CE4C56
|
|
|
|
P 8450 3100
|
|
|
|
F 0 "R29" V 8243 3100 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 3100 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 3100 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 3100 50 0001 C CNN
|
|
|
|
1 8450 3100
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
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|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R30
|
|
|
|
U 1 1 60CE4C50
|
|
|
|
P 8450 3200
|
|
|
|
F 0 "R30" V 8243 3200 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 3200 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 3200 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 3200 50 0001 C CNN
|
|
|
|
1 8450 3200
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
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|
|
|
$EndComp
|
|
|
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$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R71
|
|
|
|
U 1 1 60CE4C4A
|
|
|
|
P 9250 3100
|
|
|
|
F 0 "R71" V 9043 3100 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 3100 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 3100 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 3100 50 0001 C CNN
|
|
|
|
1 9250 3100
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
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|
|
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$EndComp
|
|
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|
Wire Wire Line
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2021-06-24 15:18:57 +08:00
|
|
|
9450 3200 9450 3100
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2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
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|
|
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Text HLabel 8650 3100 2 50 Input ~ 0
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|
|
FPGA_EEM1_1_N
|
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 3100 9100 3100
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 3200 9450 3200
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Text HLabel 8650 3200 2 50 Input ~ 0
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FPGA_EEM1_1_P
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
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|
|
L Device:R R31
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|
|
|
U 1 1 60CE4C3C
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|
|
|
P 8450 3300
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F 0 "R31" V 8243 3300 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 3300 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 3300 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 3300 50 0001 C CNN
|
|
|
|
1 8450 3300
|
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0 1 1 0
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|
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$Comp
|
2021-06-24 15:18:57 +08:00
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|
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L Device:R R32
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|
|
|
U 1 1 60CE4C36
|
|
|
|
P 8450 3400
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|
|
F 0 "R32" V 8243 3400 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 3400 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 3400 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 3400 50 0001 C CNN
|
|
|
|
1 8450 3400
|
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|
|
0 1 1 0
|
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|
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|
|
|
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$Comp
|
2021-06-24 15:18:57 +08:00
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|
|
L Device:R R72
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|
|
|
U 1 1 60CE4C30
|
|
|
|
P 9250 3300
|
|
|
|
F 0 "R72" V 9043 3300 50 0000 C CNN
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|
|
|
F 1 "100/1%" V 9134 3300 50 0000 C CNN
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|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 3300 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 3300 50 0001 C CNN
|
|
|
|
1 9250 3300
|
2021-06-16 17:13:34 +08:00
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|
|
0 1 1 0
|
|
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$EndComp
|
|
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Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 3400 9450 3300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 3300 9400 3300
|
|
|
|
Text HLabel 8650 3300 2 50 Input ~ 0
|
|
|
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FPGA_EEM1_2_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 3300 9100 3300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 3400 9450 3400
|
|
|
|
Text HLabel 8650 3400 2 50 Input ~ 0
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|
|
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FPGA_EEM1_2_P
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R33
|
|
|
|
U 1 1 60CE4C24
|
|
|
|
P 8450 3500
|
|
|
|
F 0 "R33" V 8243 3500 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 3500 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 3500 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 3500 50 0001 C CNN
|
|
|
|
1 8450 3500
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R34
|
|
|
|
U 1 1 60CE4C1E
|
|
|
|
P 8450 3600
|
|
|
|
F 0 "R34" V 8243 3600 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 3600 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 3600 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 3600 50 0001 C CNN
|
|
|
|
1 8450 3600
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R73
|
|
|
|
U 1 1 60CE4C18
|
|
|
|
P 9250 3500
|
|
|
|
F 0 "R73" V 9043 3500 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 3500 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 3500 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 3500 50 0001 C CNN
|
|
|
|
1 9250 3500
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 3600 9450 3500
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 3500 9400 3500
|
|
|
|
Text HLabel 8650 3500 2 50 Input ~ 0
|
|
|
|
FPGA_EEM1_3_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 3500 9100 3500
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 3600 9450 3600
|
|
|
|
Text HLabel 8650 3600 2 50 Input ~ 0
|
|
|
|
FPGA_EEM1_3_P
|
|
|
|
$Comp
|
|
|
|
L Device:R R35
|
|
|
|
U 1 1 60CE4C08
|
|
|
|
P 8450 3700
|
|
|
|
F 0 "R35" V 8243 3700 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 3700 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 3700 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 3700 50 0001 C CNN
|
|
|
|
1 8450 3700
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:R R36
|
|
|
|
U 1 1 60CE4C02
|
|
|
|
P 8450 3800
|
|
|
|
F 0 "R36" V 8243 3800 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 3800 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 3800 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 3800 50 0001 C CNN
|
|
|
|
1 8450 3800
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:R R74
|
|
|
|
U 1 1 60CE4BFC
|
|
|
|
P 9250 3700
|
|
|
|
F 0 "R74" V 9043 3700 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 3700 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 3700 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 3700 50 0001 C CNN
|
|
|
|
1 9250 3700
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 3800 9450 3700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 3700 9400 3700
|
|
|
|
Text HLabel 8650 3700 2 50 Input ~ 0
|
|
|
|
FPGA_EEM1_4_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 3700 9100 3700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 3800 9450 3800
|
|
|
|
Text HLabel 8650 3800 2 50 Input ~ 0
|
|
|
|
FPGA_EEM1_4_P
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R37
|
|
|
|
U 1 1 60CE4BEE
|
|
|
|
P 8450 3900
|
|
|
|
F 0 "R37" V 8243 3900 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 3900 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 3900 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 3900 50 0001 C CNN
|
|
|
|
1 8450 3900
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R38
|
|
|
|
U 1 1 60CE4BE8
|
|
|
|
P 8450 4000
|
|
|
|
F 0 "R38" V 8243 4000 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 4000 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 4000 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 4000 50 0001 C CNN
|
|
|
|
1 8450 4000
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R75
|
|
|
|
U 1 1 60CE4BE2
|
|
|
|
P 9250 3900
|
|
|
|
F 0 "R75" V 9043 3900 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 3900 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 3900 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 3900 50 0001 C CNN
|
|
|
|
1 9250 3900
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 4000 9450 3900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 3900 9400 3900
|
|
|
|
Text HLabel 8650 3900 2 50 Input ~ 0
|
|
|
|
FPGA_EEM1_5_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 3900 9100 3900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 4000 9450 4000
|
|
|
|
Text HLabel 8650 4000 2 50 Input ~ 0
|
|
|
|
FPGA_EEM1_5_P
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R39
|
|
|
|
U 1 1 60CE4BD4
|
|
|
|
P 8450 4100
|
|
|
|
F 0 "R39" V 8243 4100 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 4100 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 4100 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 4100 50 0001 C CNN
|
|
|
|
1 8450 4100
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R40
|
|
|
|
U 1 1 60CE4BCE
|
|
|
|
P 8450 4200
|
|
|
|
F 0 "R40" V 8243 4200 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 4200 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 4200 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 4200 50 0001 C CNN
|
|
|
|
1 8450 4200
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R76
|
|
|
|
U 1 1 60CE4BC8
|
|
|
|
P 9250 4100
|
|
|
|
F 0 "R76" V 9043 4100 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 4100 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 4100 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 4100 50 0001 C CNN
|
|
|
|
1 9250 4100
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 4200 9450 4100
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 4100 9400 4100
|
|
|
|
Text HLabel 8650 4100 2 50 Input ~ 0
|
|
|
|
FPGA_EEM1_6_N
|
|
|
|
Wire Wire Line
|
|
|
|
8600 4100 9100 4100
|
|
|
|
Wire Wire Line
|
|
|
|
8600 4200 9450 4200
|
|
|
|
Text HLabel 8650 4200 2 50 Input ~ 0
|
|
|
|
FPGA_EEM1_6_P
|
|
|
|
$Comp
|
|
|
|
L Device:R R41
|
|
|
|
U 1 1 60CE4BBC
|
|
|
|
P 8450 4300
|
|
|
|
F 0 "R41" V 8243 4300 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 4300 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 4300 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 4300 50 0001 C CNN
|
|
|
|
1 8450 4300
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:R R42
|
|
|
|
U 1 1 60CE4BB6
|
|
|
|
P 8450 4400
|
|
|
|
F 0 "R42" V 8243 4400 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 4400 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 4400 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 4400 50 0001 C CNN
|
|
|
|
1 8450 4400
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:R R77
|
|
|
|
U 1 1 60CE4BB0
|
|
|
|
P 9250 4300
|
|
|
|
F 0 "R77" V 9043 4300 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 4300 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 4300 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 4300 50 0001 C CNN
|
|
|
|
1 9250 4300
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 4400 9450 4300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 4300 9400 4300
|
|
|
|
Text HLabel 8650 4300 2 50 Input ~ 0
|
|
|
|
FPGA_EEM1_7_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 4300 9100 4300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 4400 9450 4400
|
|
|
|
Text HLabel 8650 4400 2 50 Input ~ 0
|
|
|
|
FPGA_EEM1_7_P
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R27
|
|
|
|
U 1 1 60CE4BA0
|
|
|
|
P 8450 2900
|
|
|
|
F 0 "R27" V 8243 2900 50 0000 C CNN
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|
|
|
F 1 "140/1%" V 8334 2900 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 2900 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 2900 50 0001 C CNN
|
|
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|
1 8450 2900
|
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|
0 1 1 0
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|
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|
|
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$Comp
|
2021-06-24 15:18:57 +08:00
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L Device:R R28
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|
U 1 1 60CE4B9A
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|
|
|
P 8450 3000
|
|
|
|
F 0 "R28" V 8243 3000 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 3000 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 3000 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 3000 50 0001 C CNN
|
|
|
|
1 8450 3000
|
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|
0 1 1 0
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|
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$Comp
|
2021-06-24 15:18:57 +08:00
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L Device:R R70
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|
U 1 1 60CE4B94
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|
|
|
P 9250 2900
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|
F 0 "R70" V 9043 2900 50 0000 C CNN
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|
|
|
F 1 "100/1%" V 9134 2900 50 0000 C CNN
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|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 2900 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 2900 50 0001 C CNN
|
|
|
|
1 9250 2900
|
2021-06-16 17:13:34 +08:00
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|
|
0 1 1 0
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Wire Wire Line
|
2021-06-24 15:18:57 +08:00
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|
|
9450 3000 9450 2900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
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|
|
9450 2900 9400 2900
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Text HLabel 8650 2900 2 50 Input ~ 0
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FPGA_EEM1_0_N
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Wire Wire Line
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8600 2900 9100 2900
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|
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Wire Wire Line
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|
8600 3000 9450 3000
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Text HLabel 8650 3000 2 50 Input ~ 0
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FPGA_EEM1_0_P
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$Comp
|
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L Device:R R13
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U 1 1 61390A34
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|
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P 8450 1300
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|
|
|
F 0 "R13" V 8243 1300 50 0000 C CNN
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|
|
|
F 1 "140/1%" V 8334 1300 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 1300 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 1300 50 0001 C CNN
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|
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1 8450 1300
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|
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0 1 1 0
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$EndComp
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$Comp
|
|
|
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L Device:R R14
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|
|
U 1 1 613952D3
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|
|
|
P 8450 1400
|
|
|
|
F 0 "R14" V 8243 1400 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 1400 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 1400 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 1400 50 0001 C CNN
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|
|
|
1 8450 1400
|
|
|
|
0 1 1 0
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|
|
|
$EndComp
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|
|
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$Comp
|
|
|
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L Device:R R63
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|
|
|
U 1 1 613AEA51
|
|
|
|
P 9250 1300
|
|
|
|
F 0 "R63" V 9043 1300 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 1300 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 1300 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 1300 50 0001 C CNN
|
|
|
|
1 9250 1300
|
|
|
|
0 1 1 0
|
|
|
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$EndComp
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 1400 9450 1300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 1300 9400 1300
|
|
|
|
Text HLabel 8650 1300 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_1_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 1300 9100 1300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 1400 9450 1400
|
|
|
|
Text HLabel 8650 1400 2 50 Input ~ 0
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|
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|
FPGA_EEM0_1_P
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R15
|
|
|
|
U 1 1 614580DC
|
|
|
|
P 8450 1500
|
|
|
|
F 0 "R15" V 8243 1500 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 1500 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 1500 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 1500 50 0001 C CNN
|
|
|
|
1 8450 1500
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R16
|
|
|
|
U 1 1 614580E2
|
|
|
|
P 8450 1600
|
|
|
|
F 0 "R16" V 8243 1600 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 1600 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 1600 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 1600 50 0001 C CNN
|
|
|
|
1 8450 1600
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R64
|
|
|
|
U 1 1 614580E8
|
|
|
|
P 9250 1500
|
|
|
|
F 0 "R64" V 9043 1500 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 1500 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 1500 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 1500 50 0001 C CNN
|
|
|
|
1 9250 1500
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 1600 9450 1500
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 1500 9400 1500
|
|
|
|
Text HLabel 8650 1500 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_2_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 1500 9100 1500
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 1600 9450 1600
|
|
|
|
Text HLabel 8650 1600 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_2_P
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R17
|
|
|
|
U 1 1 6145E7A3
|
|
|
|
P 8450 1700
|
|
|
|
F 0 "R17" V 8243 1700 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 1700 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 1700 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 1700 50 0001 C CNN
|
|
|
|
1 8450 1700
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R18
|
|
|
|
U 1 1 6145E7A9
|
|
|
|
P 8450 1800
|
|
|
|
F 0 "R18" V 8243 1800 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 1800 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 1800 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 1800 50 0001 C CNN
|
|
|
|
1 8450 1800
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R65
|
|
|
|
U 1 1 6145E7AF
|
|
|
|
P 9250 1700
|
|
|
|
F 0 "R65" V 9043 1700 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 1700 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 1700 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 1700 50 0001 C CNN
|
|
|
|
1 9250 1700
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 1800 9450 1700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 1700 9400 1700
|
|
|
|
Text HLabel 8650 1700 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_3_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 1700 9100 1700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 1800 9450 1800
|
|
|
|
Text HLabel 8650 1800 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_3_P
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R19
|
|
|
|
U 1 1 614C2784
|
|
|
|
P 8450 1900
|
|
|
|
F 0 "R19" V 8243 1900 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 1900 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 1900 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 1900 50 0001 C CNN
|
|
|
|
1 8450 1900
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R20
|
|
|
|
U 1 1 614C278A
|
|
|
|
P 8450 2000
|
|
|
|
F 0 "R20" V 8243 2000 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 2000 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 2000 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 2000 50 0001 C CNN
|
|
|
|
1 8450 2000
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R66
|
|
|
|
U 1 1 614C2790
|
|
|
|
P 9250 1900
|
|
|
|
F 0 "R66" V 9043 1900 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 1900 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 1900 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 1900 50 0001 C CNN
|
|
|
|
1 9250 1900
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 2000 9450 1900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 1900 9400 1900
|
|
|
|
Text HLabel 8650 1900 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_4_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 1900 9100 1900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 2000 9450 2000
|
|
|
|
Text HLabel 8650 2000 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_4_P
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R21
|
|
|
|
U 1 1 614E8180
|
|
|
|
P 8450 2100
|
|
|
|
F 0 "R21" V 8243 2100 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 2100 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 2100 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 2100 50 0001 C CNN
|
|
|
|
1 8450 2100
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R22
|
|
|
|
U 1 1 614E8186
|
|
|
|
P 8450 2200
|
|
|
|
F 0 "R22" V 8243 2200 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 2200 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 2200 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 2200 50 0001 C CNN
|
|
|
|
1 8450 2200
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R67
|
|
|
|
U 1 1 614E818C
|
|
|
|
P 9250 2100
|
|
|
|
F 0 "R67" V 9043 2100 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 2100 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 2100 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 2100 50 0001 C CNN
|
|
|
|
1 9250 2100
|
2021-06-16 17:13:34 +08:00
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
2021-06-24 15:18:57 +08:00
|
|
|
Wire Wire Line
|
|
|
|
9450 2200 9450 2100
|
|
|
|
Wire Wire Line
|
|
|
|
9450 2100 9400 2100
|
|
|
|
Text HLabel 8650 2100 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_5_N
|
|
|
|
Wire Wire Line
|
|
|
|
8600 2100 9100 2100
|
|
|
|
Wire Wire Line
|
|
|
|
8600 2200 9450 2200
|
|
|
|
Text HLabel 8650 2200 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_5_P
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R23
|
|
|
|
U 1 1 614E819A
|
|
|
|
P 8450 2300
|
|
|
|
F 0 "R23" V 8243 2300 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 2300 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 2300 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 2300 50 0001 C CNN
|
|
|
|
1 8450 2300
|
|
|
|
0 1 1 0
|
2021-06-16 17:13:34 +08:00
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R24
|
|
|
|
U 1 1 614E81A0
|
|
|
|
P 8450 2400
|
|
|
|
F 0 "R24" V 8243 2400 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 2400 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 2400 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 2400 50 0001 C CNN
|
|
|
|
1 8450 2400
|
|
|
|
0 1 1 0
|
2021-06-16 17:13:34 +08:00
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L Device:R R68
|
|
|
|
U 1 1 614E81A6
|
|
|
|
P 9250 2300
|
|
|
|
F 0 "R68" V 9043 2300 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 2300 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 2300 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 2300 50 0001 C CNN
|
|
|
|
1 9250 2300
|
|
|
|
0 1 1 0
|
2021-06-16 17:13:34 +08:00
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 2400 9450 2300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 2300 9400 2300
|
|
|
|
Text HLabel 8650 2300 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_6_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 2300 9100 2300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 2400 9450 2400
|
|
|
|
Text HLabel 8650 2400 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_6_P
|
|
|
|
$Comp
|
|
|
|
L Device:R R25
|
|
|
|
U 1 1 614E81B2
|
|
|
|
P 8450 2500
|
|
|
|
F 0 "R25" V 8243 2500 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 2500 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 2500 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 2500 50 0001 C CNN
|
|
|
|
1 8450 2500
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:R R26
|
|
|
|
U 1 1 614E81B8
|
|
|
|
P 8450 2600
|
|
|
|
F 0 "R26" V 8243 2600 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 2600 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 2600 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 2600 50 0001 C CNN
|
|
|
|
1 8450 2600
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:R R69
|
|
|
|
U 1 1 614E81BE
|
|
|
|
P 9250 2500
|
|
|
|
F 0 "R69" V 9043 2500 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 2500 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 2500 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 2500 50 0001 C CNN
|
|
|
|
1 9250 2500
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 2600 9450 2500
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 2500 9400 2500
|
|
|
|
Text HLabel 8650 2500 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_7_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 2500 9100 2500
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 2600 9450 2600
|
|
|
|
Text HLabel 8650 2600 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_7_P
|
|
|
|
$Comp
|
|
|
|
L Device:R R11
|
|
|
|
U 1 1 614E81CE
|
|
|
|
P 8450 1100
|
|
|
|
F 0 "R11" V 8243 1100 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 1100 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 1100 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 1100 50 0001 C CNN
|
|
|
|
1 8450 1100
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:R R12
|
|
|
|
U 1 1 614E81D4
|
|
|
|
P 8450 1200
|
|
|
|
F 0 "R12" V 8243 1200 50 0000 C CNN
|
|
|
|
F 1 "140/1%" V 8334 1200 50 0000 C CNN
|
2021-06-30 14:59:13 +08:00
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 8380 1200 50 0001 C CNN
|
2021-06-24 15:18:57 +08:00
|
|
|
F 3 "~" H 8450 1200 50 0001 C CNN
|
|
|
|
1 8450 1200
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:R R62
|
|
|
|
U 1 1 614E81DA
|
|
|
|
P 9250 1100
|
|
|
|
F 0 "R62" V 9043 1100 50 0000 C CNN
|
|
|
|
F 1 "100/1%" V 9134 1100 50 0000 C CNN
|
|
|
|
F 2 "Resistor_SMD:R_0402_1005Metric" V 9180 1100 50 0001 C CNN
|
|
|
|
F 3 "~" H 9250 1100 50 0001 C CNN
|
|
|
|
1 9250 1100
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 1200 9450 1100
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
9450 1100 9400 1100
|
|
|
|
Text HLabel 8650 1100 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_0_N
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 1100 9100 1100
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8600 1200 9450 1200
|
|
|
|
Text HLabel 8650 1200 2 50 Input ~ 0
|
|
|
|
FPGA_EEM0_0_P
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 6100 10950 6100
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 6000 10950 6000
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 3900 10950 3900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 3800 10950 3800
|
|
|
|
Text Label 10950 6100 0 50 ~ 0
|
|
|
|
GNDPLL1
|
|
|
|
Text Label 10950 3900 0 50 ~ 0
|
|
|
|
VCCPLL1
|
|
|
|
Text Label 10950 6000 0 50 ~ 0
|
|
|
|
GNDPLL0
|
|
|
|
Text Label 10950 3800 0 50 ~ 0
|
|
|
|
VCCPLL0
|
|
|
|
$Comp
|
|
|
|
L power:+3V3 #PWR024
|
|
|
|
U 1 1 611127A5
|
|
|
|
P 11050 3650
|
|
|
|
F 0 "#PWR024" H 11050 3500 50 0001 C CNN
|
|
|
|
F 1 "+3V3" V 11065 3778 50 0000 L CNN
|
|
|
|
F 2 "" H 11050 3650 50 0001 C CNN
|
|
|
|
F 3 "" H 11050 3650 50 0001 C CNN
|
|
|
|
1 11050 3650
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L power:+2V5 #PWR023
|
|
|
|
U 1 1 61110124
|
|
|
|
P 11050 3150
|
|
|
|
F 0 "#PWR023" H 11050 3000 50 0001 C CNN
|
|
|
|
F 1 "+2V5" V 11065 3278 50 0000 L CNN
|
|
|
|
F 2 "" H 11050 3150 50 0001 C CNN
|
|
|
|
F 3 "" H 11050 3150 50 0001 C CNN
|
|
|
|
1 11050 3150
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L power:+3V3 #PWR022
|
|
|
|
U 1 1 6110BA58
|
|
|
|
P 11050 2700
|
|
|
|
F 0 "#PWR022" H 11050 2550 50 0001 C CNN
|
|
|
|
F 1 "+3V3" V 11065 2828 50 0000 L CNN
|
|
|
|
F 2 "" H 11050 2700 50 0001 C CNN
|
|
|
|
F 3 "" H 11050 2700 50 0001 C CNN
|
|
|
|
1 11050 2700
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L power:+3V3 #PWR021
|
|
|
|
U 1 1 6110AE73
|
|
|
|
P 11050 2350
|
|
|
|
F 0 "#PWR021" H 11050 2200 50 0001 C CNN
|
|
|
|
F 1 "+3V3" V 11065 2478 50 0000 L CNN
|
|
|
|
F 2 "" H 11050 2350 50 0001 C CNN
|
|
|
|
F 3 "" H 11050 2350 50 0001 C CNN
|
|
|
|
1 11050 2350
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L power:+2V5 #PWR019
|
|
|
|
U 1 1 6110673B
|
|
|
|
P 11050 1600
|
|
|
|
F 0 "#PWR019" H 11050 1450 50 0001 C CNN
|
|
|
|
F 1 "+2V5" V 11065 1728 50 0000 L CNN
|
|
|
|
F 2 "" H 11050 1600 50 0001 C CNN
|
|
|
|
F 3 "" H 11050 1600 50 0001 C CNN
|
|
|
|
1 11050 1600
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L power:+3V3 #PWR020
|
|
|
|
U 1 1 610FFF53
|
|
|
|
P 11050 1900
|
|
|
|
F 0 "#PWR020" H 11050 1750 50 0001 C CNN
|
|
|
|
F 1 "+3V3" V 11065 2028 50 0000 L CNN
|
|
|
|
F 2 "" H 11050 1900 50 0001 C CNN
|
|
|
|
F 3 "" H 11050 1900 50 0001 C CNN
|
|
|
|
1 11050 1900
|
|
|
|
0 1 1 0
|
|
|
|
$EndComp
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 2000 10950 2100
|
|
|
|
Connection ~ 10950 2000
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 2000 10950 2000
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 2100 10950 2200
|
|
|
|
Connection ~ 10950 2100
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 2100 10950 2100
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 2200 10850 2200
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 1900 10950 2000
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 1900 10950 1900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 2450 10950 2550
|
|
|
|
Connection ~ 10950 2450
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 2450 10950 2450
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 2550 10850 2550
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 2350 10950 2450
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 2350 10950 2350
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 2800 10950 2900
|
|
|
|
Connection ~ 10950 2800
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 2800 10950 2800
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 2900 10950 3000
|
|
|
|
Connection ~ 10950 2900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 2900 10950 2900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 3000 10850 3000
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 2700 10950 2800
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 2700 10950 2700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 3350 10950 3450
|
|
|
|
Connection ~ 10950 3350
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 3350 10950 3350
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 3250 10950 3350
|
|
|
|
Connection ~ 10950 3250
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 3250 10950 3250
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 3450 10850 3450
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 3150 10950 3250
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 3150 10950 3150
|
2021-06-16 17:13:34 +08:00
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L power:+1V2 #PWR018
|
|
|
|
U 1 1 61088FD2
|
|
|
|
P 11050 900
|
|
|
|
F 0 "#PWR018" H 11050 750 50 0001 C CNN
|
|
|
|
F 1 "+1V2" V 11065 1028 50 0000 L CNN
|
|
|
|
F 2 "" H 11050 900 50 0001 C CNN
|
|
|
|
F 3 "" H 11050 900 50 0001 C CNN
|
|
|
|
1 11050 900
|
|
|
|
0 1 1 0
|
2021-06-16 17:13:34 +08:00
|
|
|
$EndComp
|
|
|
|
$Comp
|
2021-06-24 15:18:57 +08:00
|
|
|
L power:GND #PWR025
|
|
|
|
U 1 1 61087D3E
|
|
|
|
P 11050 4100
|
|
|
|
F 0 "#PWR025" H 11050 3850 50 0001 C CNN
|
|
|
|
F 1 "GND" V 11055 3972 50 0000 R CNN
|
|
|
|
F 2 "" H 11050 4100 50 0001 C CNN
|
|
|
|
F 3 "" H 11050 4100 50 0001 C CNN
|
|
|
|
1 11050 4100
|
|
|
|
0 -1 -1 0
|
2021-06-16 17:13:34 +08:00
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 4200 10950 4300
|
|
|
|
Connection ~ 10950 4200
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 4200 10950 4200
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 4300 10950 4400
|
|
|
|
Connection ~ 10950 4300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 4300 10950 4300
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 4400 10950 4500
|
|
|
|
Connection ~ 10950 4400
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 4400 10950 4400
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 4500 10950 4600
|
|
|
|
Connection ~ 10950 4500
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 4500 10950 4500
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 4600 10950 4700
|
|
|
|
Connection ~ 10950 4600
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 4600 10950 4600
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 4700 10950 4800
|
|
|
|
Connection ~ 10950 4700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 4700 10950 4700
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 4800 10950 4900
|
|
|
|
Connection ~ 10950 4800
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 4800 10950 4800
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 4900 10950 5000
|
|
|
|
Connection ~ 10950 4900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 4900 10950 4900
|
2021-06-16 17:13:34 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 5000 10950 5100
|
|
|
|
Connection ~ 10950 5000
|
2021-06-17 17:33:12 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 5000 10950 5000
|
2021-06-17 17:33:12 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 5100 10950 5200
|
|
|
|
Connection ~ 10950 5100
|
|
|
|
Wire Wire Line
|
|
|
|
10850 5100 10950 5100
|
|
|
|
Wire Wire Line
|
|
|
|
10950 5200 10950 5300
|
|
|
|
Connection ~ 10950 5200
|
|
|
|
Wire Wire Line
|
|
|
|
10850 5200 10950 5200
|
|
|
|
Wire Wire Line
|
|
|
|
10950 5300 10950 5400
|
|
|
|
Connection ~ 10950 5300
|
|
|
|
Wire Wire Line
|
|
|
|
10850 5300 10950 5300
|
|
|
|
Wire Wire Line
|
|
|
|
10950 5400 10950 5500
|
|
|
|
Connection ~ 10950 5400
|
|
|
|
Wire Wire Line
|
|
|
|
10850 5400 10950 5400
|
|
|
|
Wire Wire Line
|
|
|
|
10850 5600 10950 5600
|
|
|
|
Wire Wire Line
|
|
|
|
10950 5500 10950 5600
|
|
|
|
Connection ~ 10950 5500
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 5500 10950 5500
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 5600 10950 5700
|
|
|
|
Connection ~ 10950 5600
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 5700 10950 5800
|
|
|
|
Connection ~ 10950 5700
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 5700 10950 5700
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 5800 10850 5800
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 4100 10950 4200
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 4100 10950 4100
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10950 1000 10950 1100
|
|
|
|
Connection ~ 10950 1000
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 1000 10950 1000
|
|
|
|
Wire Wire Line
|
|
|
|
10950 1100 10950 1200
|
|
|
|
Connection ~ 10950 1100
|
|
|
|
Wire Wire Line
|
|
|
|
10850 1100 10950 1100
|
|
|
|
Wire Wire Line
|
|
|
|
10950 1200 10950 1300
|
|
|
|
Connection ~ 10950 1200
|
|
|
|
Wire Wire Line
|
|
|
|
10850 1200 10950 1200
|
|
|
|
Wire Wire Line
|
|
|
|
10950 1300 10950 1400
|
|
|
|
Connection ~ 10950 1300
|
|
|
|
Wire Wire Line
|
|
|
|
10850 1300 10950 1300
|
|
|
|
Wire Wire Line
|
|
|
|
10950 1400 10850 1400
|
|
|
|
Wire Wire Line
|
|
|
|
10950 900 10950 1000
|
|
|
|
Wire Wire Line
|
|
|
|
10850 900 10950 900
|
|
|
|
Text Label 8150 1100 0 50 ~ 0
|
|
|
|
LVDS0_0_P
|
|
|
|
Text Label 8150 1200 0 50 ~ 0
|
|
|
|
LVDS0_0_N
|
|
|
|
Text Label 8150 1300 0 50 ~ 0
|
|
|
|
LVDS0_1_P
|
|
|
|
Text Label 8150 1400 0 50 ~ 0
|
|
|
|
LVDS0_1_N
|
|
|
|
Text Label 8150 1500 0 50 ~ 0
|
|
|
|
LVDS0_2_P
|
|
|
|
Text Label 8150 1600 0 50 ~ 0
|
|
|
|
LVDS0_2_N
|
|
|
|
Text Label 8150 1700 0 50 ~ 0
|
|
|
|
LVDS0_3_P
|
|
|
|
Text Label 8150 1800 0 50 ~ 0
|
|
|
|
LVDS0_3_N
|
|
|
|
Text Label 8150 1900 0 50 ~ 0
|
|
|
|
LVDS0_4_P
|
|
|
|
Text Label 8150 2000 0 50 ~ 0
|
|
|
|
LVDS0_4_N
|
|
|
|
Text Label 8150 2100 0 50 ~ 0
|
|
|
|
LVDS0_5_P
|
|
|
|
Text Label 8150 2200 0 50 ~ 0
|
|
|
|
LVDS0_5_N
|
|
|
|
Text Label 8150 2300 0 50 ~ 0
|
|
|
|
LVDS0_6_P
|
|
|
|
Text Label 8150 2400 0 50 ~ 0
|
|
|
|
LVDS0_6_N
|
|
|
|
Text Label 8150 2500 0 50 ~ 0
|
|
|
|
LVDS0_7_P
|
|
|
|
Text Label 8150 2600 0 50 ~ 0
|
|
|
|
LVDS0_7_N
|
|
|
|
Text Label 8150 2900 0 50 ~ 0
|
|
|
|
LVDS1_0_P
|
|
|
|
Text Label 8150 3000 0 50 ~ 0
|
|
|
|
LVDS1_0_N
|
|
|
|
Text Label 8150 3100 0 50 ~ 0
|
|
|
|
LVDS1_1_P
|
|
|
|
Text Label 8150 3200 0 50 ~ 0
|
|
|
|
LVDS1_1_N
|
|
|
|
Text Label 8150 3300 0 50 ~ 0
|
|
|
|
LVDS1_2_P
|
|
|
|
Text Label 8150 3400 0 50 ~ 0
|
|
|
|
LVDS1_2_N
|
|
|
|
Text Label 8150 3500 0 50 ~ 0
|
|
|
|
LVDS1_3_P
|
|
|
|
Text Label 8150 3600 0 50 ~ 0
|
|
|
|
LVDS1_3_N
|
|
|
|
Text Label 8150 3700 0 50 ~ 0
|
|
|
|
LVDS1_4_P
|
|
|
|
Text Label 8150 3800 0 50 ~ 0
|
|
|
|
LVDS1_4_N
|
|
|
|
Text Label 8150 3900 0 50 ~ 0
|
|
|
|
LVDS1_5_P
|
|
|
|
Text Label 8150 4000 0 50 ~ 0
|
|
|
|
LVDS1_5_N
|
|
|
|
Text Label 8150 4100 0 50 ~ 0
|
|
|
|
LVDS1_6_P
|
|
|
|
Text Label 8150 4200 0 50 ~ 0
|
|
|
|
LVDS1_6_N
|
|
|
|
Text Label 8150 4300 0 50 ~ 0
|
|
|
|
LVDS1_7_P
|
|
|
|
Text Label 8150 4400 0 50 ~ 0
|
|
|
|
LVDS1_7_N
|
|
|
|
Text Label 8150 4700 0 50 ~ 0
|
|
|
|
LVDS2_0_P
|
|
|
|
Text Label 8150 4800 0 50 ~ 0
|
|
|
|
LVDS2_0_N
|
|
|
|
Text Label 8150 4900 0 50 ~ 0
|
|
|
|
LVDS2_1_P
|
|
|
|
Text Label 8150 5000 0 50 ~ 0
|
|
|
|
LVDS2_1_N
|
|
|
|
Text Label 8150 5100 0 50 ~ 0
|
|
|
|
LVDS2_2_P
|
|
|
|
Text Label 8150 5200 0 50 ~ 0
|
|
|
|
LVDS2_2_N
|
|
|
|
Text Label 8150 5300 0 50 ~ 0
|
|
|
|
LVDS2_3_P
|
|
|
|
Text Label 8150 5400 0 50 ~ 0
|
|
|
|
LVDS2_3_N
|
|
|
|
Text Label 8150 5500 0 50 ~ 0
|
|
|
|
LVDS2_4_P
|
|
|
|
Text Label 8150 5600 0 50 ~ 0
|
|
|
|
LVDS2_4_N
|
|
|
|
Text Label 8150 5700 0 50 ~ 0
|
|
|
|
LVDS2_5_P
|
|
|
|
Text Label 8150 5800 0 50 ~ 0
|
|
|
|
LVDS2_5_N
|
|
|
|
Text Label 8150 5900 0 50 ~ 0
|
|
|
|
LVDS2_6_P
|
|
|
|
Text Label 8150 6000 0 50 ~ 0
|
|
|
|
LVDS2_6_N
|
|
|
|
Text Label 8150 6100 0 50 ~ 0
|
|
|
|
LVDS2_7_P
|
|
|
|
Text Label 8150 6200 0 50 ~ 0
|
|
|
|
LVDS2_7_N
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
10850 3650 11050 3650
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
11050 4100 10950 4100
|
|
|
|
Connection ~ 10950 4100
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
11050 3150 10950 3150
|
|
|
|
Connection ~ 10950 3150
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
11050 2700 10950 2700
|
|
|
|
Connection ~ 10950 2700
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
11050 2350 10950 2350
|
|
|
|
Connection ~ 10950 2350
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
11050 1900 10950 1900
|
|
|
|
Connection ~ 10950 1900
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
11050 1600 10850 1600
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
11050 900 10950 900
|
|
|
|
Connection ~ 10950 900
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 3700 8300 3700
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 3800 8300 3800
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 4900 8300 4900
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 5000 8300 5000
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 5100 8300 5100
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 5200 8300 5200
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 5300 8300 5300
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 5400 8300 5400
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 5500 8300 5500
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 5600 8300 5600
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 5700 8300 5700
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 5800 8300 5800
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 5900 8300 5900
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 6000 8300 6000
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 6100 8300 6100
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 6200 8300 6200
|
2021-06-18 10:27:05 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 2900 8300 2900
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 3000 8300 3000
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 3100 8300 3100
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 3200 8300 3200
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 3300 8300 3300
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 3400 8300 3400
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 3500 8300 3500
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 3600 8300 3600
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 4100 8300 4100
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 4200 8300 4200
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 4300 8300 4300
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 4400 8300 4400
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 1100 8300 1100
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 1200 8300 1200
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 4700 8300 4700
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 4800 8300 4800
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 1300 8300 1300
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 1400 8300 1400
|
2021-06-22 16:34:02 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 1500 8300 1500
|
2021-06-21 17:06:20 +08:00
|
|
|
Wire Wire Line
|
2021-06-24 15:18:57 +08:00
|
|
|
8150 1600 8300 1600
|
|
|
|
Wire Wire Line
|
|
|
|
8150 1700 8300 1700
|
|
|
|
Wire Wire Line
|
|
|
|
8150 1800 8300 1800
|
|
|
|
Wire Wire Line
|
|
|
|
8150 1900 8300 1900
|
|
|
|
Wire Wire Line
|
|
|
|
8150 2000 8300 2000
|
|
|
|
Wire Wire Line
|
|
|
|
8150 2100 8300 2100
|
|
|
|
Wire Wire Line
|
|
|
|
8150 2200 8300 2200
|
|
|
|
Wire Wire Line
|
|
|
|
8150 2300 8300 2300
|
|
|
|
Wire Wire Line
|
|
|
|
8150 2400 8300 2400
|
|
|
|
Wire Wire Line
|
|
|
|
8150 2500 8300 2500
|
|
|
|
Wire Wire Line
|
|
|
|
8150 2600 8300 2600
|
|
|
|
Wire Wire Line
|
|
|
|
8150 3900 8300 3900
|
|
|
|
Wire Wire Line
|
|
|
|
8150 4000 8300 4000
|
|
|
|
NoConn ~ 3750 5000
|
|
|
|
NoConn ~ 3750 5500
|
|
|
|
NoConn ~ 3750 5800
|
|
|
|
NoConn ~ 3750 5900
|
|
|
|
NoConn ~ 3750 6000
|
|
|
|
NoConn ~ 3750 1800
|
|
|
|
NoConn ~ 7750 5300
|
|
|
|
NoConn ~ 7750 5400
|
|
|
|
NoConn ~ 7750 5500
|
|
|
|
NoConn ~ 7750 5600
|
|
|
|
Text Label 7750 6100 0 50 ~ 0
|
|
|
|
LVDS0_0_N
|
|
|
|
Text Label 7750 6200 0 50 ~ 0
|
|
|
|
LVDS0_0_P
|
|
|
|
Text Label 7750 5100 0 50 ~ 0
|
|
|
|
LVDS0_1_N
|
|
|
|
Text Label 7750 5200 0 50 ~ 0
|
|
|
|
LVDS0_1_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 3100 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_2_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 3200 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_2_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 4700 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_3_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 4800 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_3_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 2700 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_4_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 2800 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_4_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 4300 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_5_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 4400 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_5_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 2100 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_6_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 2200 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_6_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 3300 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_7_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 3400 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS0_7_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 5700 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_1_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 5800 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_1_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 4900 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_2_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 5000 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_2_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 4500 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_3_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 4600 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_3_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 3500 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_7_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 3600 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_7_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 2900 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_0_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 3000 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_0_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 2300 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_1_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 2400 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_1_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 1700 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_2_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 1800 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_2_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 1900 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_3_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 2000 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_3_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 1500 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_4_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 1600 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_4_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 1300 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_5_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 1400 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_5_P
|
|
|
|
Text Label 7750 2500 0 50 ~ 0
|
|
|
|
LVDS2_6_N
|
|
|
|
Text Label 7750 2600 0 50 ~ 0
|
|
|
|
LVDS2_6_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 1100 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_7_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 1200 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS2_7_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 5900 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_0_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 6000 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_0_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 3800 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_6_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 3700 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_6_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 4000 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_5_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 3900 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_5_N
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 4200 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_4_P
|
2021-07-06 10:28:18 +08:00
|
|
|
Text Label 7750 4100 0 50 ~ 0
|
2021-06-24 15:18:57 +08:00
|
|
|
LVDS1_4_N
|
2021-06-25 16:57:46 +08:00
|
|
|
Text HLabel 5850 2500 2 50 Input ~ 0
|
|
|
|
FPGA_IO0
|
|
|
|
Wire Wire Line
|
|
|
|
5850 2500 5750 2500
|
|
|
|
Text HLabel 5850 3000 2 50 Input ~ 0
|
|
|
|
FPGA_IO1
|
|
|
|
Wire Wire Line
|
|
|
|
5750 3000 5850 3000
|
|
|
|
Text HLabel 3850 2800 2 50 Input ~ 0
|
|
|
|
FPGA_ADC_D0
|
|
|
|
Wire Wire Line
|
|
|
|
3850 2800 3750 2800
|
|
|
|
Text Label 5850 4400 0 50 ~ 0
|
|
|
|
FPGA_LED
|
|
|
|
Text Label 5850 5000 0 50 ~ 0
|
|
|
|
FPGA_KEY
|
|
|
|
Wire Wire Line
|
|
|
|
5850 4400 5750 4400
|
|
|
|
Wire Wire Line
|
|
|
|
5750 5000 5850 5000
|
2021-07-07 16:14:10 +08:00
|
|
|
Text Label 11100 7350 0 50 ~ 0
|
2021-06-25 16:57:46 +08:00
|
|
|
FPGA_KEY
|
2021-07-07 16:14:10 +08:00
|
|
|
Text Label 11200 7500 0 50 ~ 0
|
2021-06-25 16:57:46 +08:00
|
|
|
FPGA_LED
|
|
|
|
Text HLabel 1850 2600 2 50 Input ~ 0
|
|
|
|
FPGA_FSMC_A2
|
|
|
|
Wire Wire Line
|
|
|
|
1850 2600 1800 2600
|
|
|
|
Text HLabel 1850 3600 2 50 Input ~ 0
|
|
|
|
FPGA_FSMC_A1
|
|
|
|
Wire Wire Line
|
|
|
|
1850 3600 1800 3600
|
|
|
|
Wire Wire Line
|
|
|
|
1850 5000 1800 5000
|
|
|
|
Text HLabel 1850 5000 2 50 Input ~ 0
|
|
|
|
FPGA_FSMC_D8
|
|
|
|
Wire Wire Line
|
|
|
|
1850 2000 1800 2000
|
|
|
|
Text HLabel 1850 2000 2 50 Input ~ 0
|
|
|
|
FPGA_FSMC_A7
|
2021-06-25 18:15:56 +08:00
|
|
|
NoConn ~ 1800 1100
|
|
|
|
NoConn ~ 1800 1400
|
|
|
|
NoConn ~ 1800 1900
|
|
|
|
NoConn ~ 1800 2100
|
|
|
|
NoConn ~ 1800 2800
|
|
|
|
NoConn ~ 1800 3000
|
|
|
|
NoConn ~ 1800 3100
|
|
|
|
NoConn ~ 1800 3300
|
|
|
|
NoConn ~ 1800 3500
|
|
|
|
NoConn ~ 1800 3700
|
|
|
|
NoConn ~ 1800 4300
|
|
|
|
NoConn ~ 1800 4400
|
|
|
|
NoConn ~ 1800 4600
|
|
|
|
NoConn ~ 1800 4900
|
|
|
|
NoConn ~ 1800 5200
|
|
|
|
NoConn ~ 1800 5400
|
|
|
|
NoConn ~ 1800 5500
|
|
|
|
NoConn ~ 1800 5700
|
|
|
|
NoConn ~ 1800 5800
|
|
|
|
NoConn ~ 1800 5900
|
|
|
|
NoConn ~ 3750 4500
|
|
|
|
NoConn ~ 3750 4400
|
|
|
|
NoConn ~ 3750 4200
|
|
|
|
NoConn ~ 3750 4100
|
|
|
|
NoConn ~ 3750 4000
|
|
|
|
NoConn ~ 3750 3800
|
|
|
|
NoConn ~ 3750 3600
|
|
|
|
NoConn ~ 3750 3300
|
|
|
|
NoConn ~ 3750 3200
|
|
|
|
NoConn ~ 3750 3100
|
|
|
|
NoConn ~ 3750 2700
|
|
|
|
NoConn ~ 3750 2600
|
|
|
|
NoConn ~ 3750 2400
|
|
|
|
NoConn ~ 3750 2200
|
|
|
|
NoConn ~ 3750 2000
|
|
|
|
NoConn ~ 3750 1900
|
|
|
|
NoConn ~ 3750 1600
|
|
|
|
NoConn ~ 3750 1500
|
|
|
|
NoConn ~ 3750 1400
|
|
|
|
NoConn ~ 3750 1100
|
|
|
|
NoConn ~ 3750 1000
|
|
|
|
NoConn ~ 3750 900
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C50
|
|
|
|
U 1 1 611CA559
|
2021-07-07 16:14:10 +08:00
|
|
|
P 1350 9650
|
|
|
|
F 0 "C50" V 1098 9650 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 1189 9650 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1388 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 1350 9650 50 0001 C CNN
|
|
|
|
1 1350 9650
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L power:GND #PWR0148
|
|
|
|
U 1 1 6120636B
|
2021-07-07 16:14:10 +08:00
|
|
|
P 1350 9900
|
|
|
|
F 0 "#PWR0148" H 1350 9650 50 0001 C CNN
|
|
|
|
F 1 "GND" V 1355 9772 50 0000 R CNN
|
|
|
|
F 2 "" H 1350 9900 50 0001 C CNN
|
|
|
|
F 3 "" H 1350 9900 50 0001 C CNN
|
|
|
|
1 1350 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1350 9800 1350 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1350 9500 1350 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L power:GND #PWR0149
|
|
|
|
U 1 1 61397A55
|
2021-07-07 16:14:10 +08:00
|
|
|
P 6850 9200
|
|
|
|
F 0 "#PWR0149" H 6850 8950 50 0001 C CNN
|
|
|
|
F 1 "GND" V 6855 9072 50 0000 R CNN
|
|
|
|
F 2 "" H 6850 9200 50 0001 C CNN
|
|
|
|
F 3 "" H 6850 9200 50 0001 C CNN
|
|
|
|
1 6850 9200
|
2021-07-02 11:04:53 +08:00
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L power:GND #PWR0150
|
|
|
|
U 1 1 613CFCA8
|
2021-07-07 16:14:10 +08:00
|
|
|
P 6850 10350
|
|
|
|
F 0 "#PWR0150" H 6850 10100 50 0001 C CNN
|
|
|
|
F 1 "GND" V 6855 10222 50 0000 R CNN
|
|
|
|
F 2 "" H 6850 10350 50 0001 C CNN
|
|
|
|
F 3 "" H 6850 10350 50 0001 C CNN
|
|
|
|
1 6850 10350
|
2021-07-02 11:04:53 +08:00
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1350 9450 1350 9400
|
2021-07-02 11:04:53 +08:00
|
|
|
NoConn ~ 5750 5200
|
|
|
|
NoConn ~ 5750 5100
|
|
|
|
NoConn ~ 5750 4900
|
|
|
|
NoConn ~ 5750 4800
|
|
|
|
NoConn ~ 5750 4600
|
|
|
|
NoConn ~ 5750 4100
|
|
|
|
NoConn ~ 5750 4000
|
|
|
|
NoConn ~ 5750 3900
|
|
|
|
NoConn ~ 5750 3700
|
|
|
|
NoConn ~ 5750 3600
|
|
|
|
NoConn ~ 5750 3400
|
|
|
|
NoConn ~ 5750 3200
|
|
|
|
NoConn ~ 5750 3100
|
|
|
|
NoConn ~ 5750 2900
|
|
|
|
NoConn ~ 5750 2800
|
|
|
|
NoConn ~ 5750 2700
|
|
|
|
NoConn ~ 5750 2600
|
|
|
|
NoConn ~ 5750 2300
|
|
|
|
NoConn ~ 5750 2200
|
|
|
|
NoConn ~ 5750 2100
|
|
|
|
NoConn ~ 5750 2000
|
|
|
|
NoConn ~ 5750 1900
|
|
|
|
NoConn ~ 5750 1500
|
|
|
|
NoConn ~ 5750 1300
|
|
|
|
NoConn ~ 5750 1100
|
|
|
|
NoConn ~ 5750 900
|
|
|
|
NoConn ~ 10850 1700
|
|
|
|
$Comp
|
|
|
|
L power:+2V5 #PWR0151
|
|
|
|
U 1 1 61E6B89D
|
2021-07-07 16:14:10 +08:00
|
|
|
P 6850 8700
|
|
|
|
F 0 "#PWR0151" H 6850 8550 50 0001 C CNN
|
|
|
|
F 1 "+2V5" V 6865 8828 50 0000 L CNN
|
|
|
|
F 2 "" H 6850 8700 50 0001 C CNN
|
|
|
|
F 3 "" H 6850 8700 50 0001 C CNN
|
|
|
|
1 6850 8700
|
2021-07-02 11:04:53 +08:00
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L power:+3V3 #PWR0152
|
|
|
|
U 1 1 61E6B8A3
|
2021-07-07 16:14:10 +08:00
|
|
|
P 1350 9400
|
|
|
|
F 0 "#PWR0152" H 1350 9250 50 0001 C CNN
|
|
|
|
F 1 "+3V3" V 1365 9528 50 0000 L CNN
|
|
|
|
F 2 "" H 1350 9400 50 0001 C CNN
|
|
|
|
F 3 "" H 1350 9400 50 0001 C CNN
|
|
|
|
1 1350 9400
|
2021-07-02 11:04:53 +08:00
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L power:+1V2 #PWR0153
|
|
|
|
U 1 1 61E6B8A9
|
2021-07-07 16:14:10 +08:00
|
|
|
P 6850 9850
|
|
|
|
F 0 "#PWR0153" H 6850 9700 50 0001 C CNN
|
|
|
|
F 1 "+1V2" V 6865 9978 50 0000 L CNN
|
|
|
|
F 2 "" H 6850 9850 50 0001 C CNN
|
|
|
|
F 3 "" H 6850 9850 50 0001 C CNN
|
|
|
|
1 6850 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
$Comp
|
|
|
|
L Device:C C56
|
|
|
|
U 1 1 62010A4C
|
2021-07-07 16:14:10 +08:00
|
|
|
P 1750 9650
|
|
|
|
F 0 "C56" V 1498 9650 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 1589 9650 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1788 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 1750 9650 50 0001 C CNN
|
|
|
|
1 1750 9650
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1750 9800 1750 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1750 9500 1750 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C59
|
|
|
|
U 1 1 6203D958
|
2021-07-07 16:14:10 +08:00
|
|
|
P 2150 9650
|
|
|
|
F 0 "C59" V 1898 9650 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 1989 9650 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 2188 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 2150 9650 50 0001 C CNN
|
|
|
|
1 2150 9650
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2150 9800 2150 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2150 9500 2150 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C62
|
|
|
|
U 1 1 6206AEA7
|
2021-07-07 16:14:10 +08:00
|
|
|
P 2550 9650
|
|
|
|
F 0 "C62" V 2298 9650 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 2389 9650 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 2588 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 2550 9650 50 0001 C CNN
|
|
|
|
1 2550 9650
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2550 9800 2550 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2550 9500 2550 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C65
|
|
|
|
U 1 1 620984B2
|
2021-07-07 16:14:10 +08:00
|
|
|
P 2950 9650
|
|
|
|
F 0 "C65" V 2698 9650 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 2789 9650 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 2988 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 2950 9650 50 0001 C CNN
|
|
|
|
1 2950 9650
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2950 9800 2950 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2950 9500 2950 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C68
|
|
|
|
U 1 1 620C5ACF
|
2021-07-07 16:14:10 +08:00
|
|
|
P 3350 9650
|
|
|
|
F 0 "C68" V 3098 9650 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 3189 9650 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 3388 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 3350 9650 50 0001 C CNN
|
|
|
|
1 3350 9650
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
3350 9800 3350 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
3350 9500 3350 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C71
|
|
|
|
U 1 1 620F3346
|
2021-07-07 16:14:10 +08:00
|
|
|
P 3750 9650
|
|
|
|
F 0 "C71" V 3498 9650 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 3589 9650 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 3788 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 3750 9650 50 0001 C CNN
|
|
|
|
1 3750 9650
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
3750 9800 3750 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
3750 9500 3750 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
3750 9450 3350 9450
|
|
|
|
Connection ~ 1350 9450
|
|
|
|
Connection ~ 1750 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1750 9450 1350 9450
|
|
|
|
Connection ~ 2150 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2150 9450 1750 9450
|
|
|
|
Connection ~ 2550 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2550 9450 2150 9450
|
|
|
|
Connection ~ 2950 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2950 9450 2550 9450
|
|
|
|
Connection ~ 3350 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
3350 9450 2950 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
3750 9850 3350 9850
|
|
|
|
Connection ~ 1350 9850
|
|
|
|
Connection ~ 1750 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1750 9850 1350 9850
|
|
|
|
Connection ~ 2150 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2150 9850 1750 9850
|
|
|
|
Connection ~ 2550 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2550 9850 2150 9850
|
|
|
|
Connection ~ 2950 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
2950 9850 2550 9850
|
|
|
|
Connection ~ 3350 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
3350 9850 2950 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C74
|
|
|
|
U 1 1 62182AD4
|
2021-07-07 16:14:10 +08:00
|
|
|
P 4150 9650
|
|
|
|
F 0 "C74" V 3898 9650 50 0000 C CNN
|
|
|
|
F 1 "0.1nF" V 3989 9650 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 4188 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 4150 9650 50 0001 C CNN
|
|
|
|
1 4150 9650
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
4150 9800 4150 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
4150 9500 4150 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C77
|
|
|
|
U 1 1 621B31B5
|
2021-07-07 16:14:10 +08:00
|
|
|
P 4550 9650
|
|
|
|
F 0 "C77" V 4298 9650 50 0000 C CNN
|
|
|
|
F 1 "0.1nF" V 4389 9650 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 4588 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 4550 9650 50 0001 C CNN
|
|
|
|
1 4550 9650
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
4550 9800 4550 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
4550 9500 4550 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
4550 9450 4150 9450
|
|
|
|
Connection ~ 3750 9450
|
|
|
|
Connection ~ 4150 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
4150 9450 3750 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
4550 9850 4150 9850
|
|
|
|
Connection ~ 3750 9850
|
|
|
|
Connection ~ 4150 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
4150 9850 3750 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C51
|
|
|
|
U 1 1 6224994D
|
2021-07-07 16:14:10 +08:00
|
|
|
P 950 9650
|
|
|
|
F 0 "C51" H 1065 9696 50 0000 L CNN
|
|
|
|
F 1 "10uF" H 1065 9605 50 0000 L CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 988 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 950 9650 50 0001 C CNN
|
|
|
|
1 950 9650
|
2021-07-02 11:04:53 +08:00
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1350 9450 950 9450
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
950 9450 950 9500
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1350 9850 950 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
950 9850 950 9800
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
1350 9850 1350 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C54
|
|
|
|
U 1 1 6249C320
|
2021-07-07 16:14:10 +08:00
|
|
|
P 6850 8950
|
|
|
|
F 0 "C54" V 6598 8950 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 6689 8950 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6888 8800 50 0001 C CNN
|
|
|
|
F 3 "~" H 6850 8950 50 0001 C CNN
|
|
|
|
1 6850 8950
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 9100 6850 9150
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 8800 6850 8750
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 8750 6850 8700
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C57
|
|
|
|
U 1 1 6249C329
|
2021-07-07 16:14:10 +08:00
|
|
|
P 7250 8950
|
|
|
|
F 0 "C57" V 6998 8950 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 7089 8950 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 7288 8800 50 0001 C CNN
|
|
|
|
F 3 "~" H 7250 8950 50 0001 C CNN
|
|
|
|
1 7250 8950
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7250 9100 7250 9150
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7250 8800 7250 8750
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C60
|
|
|
|
U 1 1 6249C331
|
2021-07-07 16:14:10 +08:00
|
|
|
P 7650 8950
|
|
|
|
F 0 "C60" V 7398 8950 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 7489 8950 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 7688 8800 50 0001 C CNN
|
|
|
|
F 3 "~" H 7650 8950 50 0001 C CNN
|
|
|
|
1 7650 8950
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7650 9100 7650 9150
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7650 8800 7650 8750
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C63
|
|
|
|
U 1 1 6249C339
|
2021-07-07 16:14:10 +08:00
|
|
|
P 8050 8950
|
|
|
|
F 0 "C63" V 7798 8950 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 7889 8950 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 8088 8800 50 0001 C CNN
|
|
|
|
F 3 "~" H 8050 8950 50 0001 C CNN
|
|
|
|
1 8050 8950
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8050 9100 8050 9150
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8050 8800 8050 8750
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C66
|
|
|
|
U 1 1 6249C341
|
2021-07-07 16:14:10 +08:00
|
|
|
P 8450 8950
|
|
|
|
F 0 "C66" V 8198 8950 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 8289 8950 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 8488 8800 50 0001 C CNN
|
|
|
|
F 3 "~" H 8450 8950 50 0001 C CNN
|
|
|
|
1 8450 8950
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8450 9100 8450 9150
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8450 8800 8450 8750
|
|
|
|
Connection ~ 6850 8750
|
|
|
|
Connection ~ 7250 8750
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7250 8750 6850 8750
|
|
|
|
Connection ~ 7650 8750
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7650 8750 7250 8750
|
|
|
|
Connection ~ 8050 8750
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8050 8750 7650 8750
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8450 8750 8050 8750
|
|
|
|
Connection ~ 6850 9150
|
|
|
|
Connection ~ 7250 9150
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7250 9150 6850 9150
|
|
|
|
Connection ~ 7650 9150
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7650 9150 7250 9150
|
|
|
|
Connection ~ 8050 9150
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8050 9150 7650 9150
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8450 9150 8050 9150
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C52
|
|
|
|
U 1 1 6249C389
|
2021-07-07 16:14:10 +08:00
|
|
|
P 6450 8950
|
|
|
|
F 0 "C52" H 6565 8996 50 0000 L CNN
|
|
|
|
F 1 "10uF" H 6565 8905 50 0000 L CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6488 8800 50 0001 C CNN
|
|
|
|
F 3 "~" H 6450 8950 50 0001 C CNN
|
|
|
|
1 6450 8950
|
2021-07-02 11:04:53 +08:00
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 8750 6450 8750
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6450 8750 6450 8800
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 9150 6450 9150
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6450 9150 6450 9100
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 9150 6850 9200
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C55
|
|
|
|
U 1 1 6258FF21
|
2021-07-07 16:14:10 +08:00
|
|
|
P 6850 10100
|
|
|
|
F 0 "C55" V 6598 10100 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 6689 10100 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6888 9950 50 0001 C CNN
|
|
|
|
F 3 "~" H 6850 10100 50 0001 C CNN
|
|
|
|
1 6850 10100
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 10250 6850 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 9950 6850 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 9900 6850 9850
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C58
|
|
|
|
U 1 1 6258FF2A
|
2021-07-07 16:14:10 +08:00
|
|
|
P 7250 10100
|
|
|
|
F 0 "C58" V 6998 10100 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 7089 10100 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 7288 9950 50 0001 C CNN
|
|
|
|
F 3 "~" H 7250 10100 50 0001 C CNN
|
|
|
|
1 7250 10100
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7250 10250 7250 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7250 9950 7250 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C61
|
|
|
|
U 1 1 6258FF32
|
2021-07-07 16:14:10 +08:00
|
|
|
P 7650 10100
|
|
|
|
F 0 "C61" V 7398 10100 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 7489 10100 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 7688 9950 50 0001 C CNN
|
|
|
|
F 3 "~" H 7650 10100 50 0001 C CNN
|
|
|
|
1 7650 10100
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7650 10250 7650 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7650 9950 7650 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C64
|
|
|
|
U 1 1 6258FF3A
|
2021-07-07 16:14:10 +08:00
|
|
|
P 8050 10100
|
|
|
|
F 0 "C64" V 7798 10100 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 7889 10100 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 8088 9950 50 0001 C CNN
|
|
|
|
F 3 "~" H 8050 10100 50 0001 C CNN
|
|
|
|
1 8050 10100
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8050 10250 8050 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8050 9950 8050 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C67
|
|
|
|
U 1 1 6258FF42
|
2021-07-07 16:14:10 +08:00
|
|
|
P 8450 10100
|
|
|
|
F 0 "C67" V 8198 10100 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 8289 10100 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 8488 9950 50 0001 C CNN
|
|
|
|
F 3 "~" H 8450 10100 50 0001 C CNN
|
|
|
|
1 8450 10100
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8450 10250 8450 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8450 9950 8450 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C70
|
|
|
|
U 1 1 6258FF4A
|
2021-07-07 16:14:10 +08:00
|
|
|
P 8850 10100
|
|
|
|
F 0 "C70" V 8598 10100 50 0000 C CNN
|
|
|
|
F 1 "0.1uF" V 8689 10100 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 8888 9950 50 0001 C CNN
|
|
|
|
F 3 "~" H 8850 10100 50 0001 C CNN
|
|
|
|
1 8850 10100
|
2021-07-02 11:04:53 +08:00
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8850 10250 8850 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8850 9950 8850 9900
|
|
|
|
Connection ~ 6850 9900
|
|
|
|
Connection ~ 7250 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7250 9900 6850 9900
|
|
|
|
Connection ~ 7650 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7650 9900 7250 9900
|
|
|
|
Connection ~ 8050 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8050 9900 7650 9900
|
|
|
|
Connection ~ 8450 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8450 9900 8050 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8850 9900 8450 9900
|
|
|
|
Connection ~ 6850 10300
|
|
|
|
Connection ~ 7250 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7250 10300 6850 10300
|
|
|
|
Connection ~ 7650 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
7650 10300 7250 10300
|
|
|
|
Connection ~ 8050 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8050 10300 7650 10300
|
|
|
|
Connection ~ 8450 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8450 10300 8050 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
8850 10300 8450 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
$Comp
|
|
|
|
L Device:C C53
|
|
|
|
U 1 1 6258FF8A
|
2021-07-07 16:14:10 +08:00
|
|
|
P 6450 10100
|
|
|
|
F 0 "C53" H 6565 10146 50 0000 L CNN
|
|
|
|
F 1 "10uF" H 6565 10055 50 0000 L CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6488 9950 50 0001 C CNN
|
|
|
|
F 3 "~" H 6450 10100 50 0001 C CNN
|
|
|
|
1 6450 10100
|
2021-07-02 11:04:53 +08:00
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 9900 6450 9900
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6450 9900 6450 9950
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 10300 6450 10300
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6450 10300 6450 10250
|
2021-07-02 11:04:53 +08:00
|
|
|
Wire Wire Line
|
2021-07-07 16:14:10 +08:00
|
|
|
6850 10300 6850 10350
|
2021-07-06 10:28:18 +08:00
|
|
|
NoConn ~ 3750 3400
|
|
|
|
NoConn ~ 3750 3700
|
|
|
|
Text Label 3800 3900 0 50 ~ 0
|
|
|
|
I2C_2_SDA
|
|
|
|
Text HLabel 3850 3900 2 50 Input ~ 0
|
|
|
|
FPGA_EEM2_IIC_SDA
|
|
|
|
Wire Wire Line
|
|
|
|
3750 3900 3850 3900
|
|
|
|
Text Label 3800 4300 0 50 ~ 0
|
|
|
|
I2C_2_SCL
|
|
|
|
Text HLabel 3850 4300 2 50 Input ~ 0
|
|
|
|
FPGA_EEM2_IIC_SCL
|
|
|
|
Wire Wire Line
|
|
|
|
3750 4300 3850 4300
|
2021-07-07 16:14:10 +08:00
|
|
|
Wire Wire Line
|
|
|
|
1800 1600 1850 1600
|
|
|
|
Text HLabel 1850 1600 2 50 Input ~ 0
|
|
|
|
FPGA_FSMC_NE1
|
|
|
|
$Comp
|
|
|
|
L Device:C C69
|
|
|
|
U 1 1 61437B16
|
|
|
|
P 4950 9650
|
|
|
|
F 0 "C69" V 4698 9650 50 0000 C CNN
|
|
|
|
F 1 "0.1nF" V 4789 9650 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 4988 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 4950 9650 50 0001 C CNN
|
|
|
|
1 4950 9650
|
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
|
|
|
4950 9800 4950 9850
|
|
|
|
Wire Wire Line
|
|
|
|
4950 9500 4950 9450
|
|
|
|
$Comp
|
|
|
|
L Device:C C72
|
|
|
|
U 1 1 61437B1E
|
|
|
|
P 5350 9650
|
|
|
|
F 0 "C72" V 5098 9650 50 0000 C CNN
|
|
|
|
F 1 "0.1nF" V 5189 9650 50 0000 C CNN
|
|
|
|
F 2 "Capacitor_SMD:C_0402_1005Metric" H 5388 9500 50 0001 C CNN
|
|
|
|
F 3 "~" H 5350 9650 50 0001 C CNN
|
|
|
|
1 5350 9650
|
|
|
|
-1 0 0 1
|
|
|
|
$EndComp
|
|
|
|
Wire Wire Line
|
|
|
|
5350 9800 5350 9850
|
|
|
|
Wire Wire Line
|
|
|
|
5350 9500 5350 9450
|
|
|
|
Wire Wire Line
|
|
|
|
5350 9450 4950 9450
|
|
|
|
Connection ~ 4950 9450
|
|
|
|
Wire Wire Line
|
|
|
|
4950 9450 4550 9450
|
|
|
|
Wire Wire Line
|
|
|
|
5350 9850 4950 9850
|
|
|
|
Connection ~ 4950 9850
|
|
|
|
Wire Wire Line
|
|
|
|
4950 9850 4550 9850
|
|
|
|
Connection ~ 4550 9450
|
|
|
|
Connection ~ 4550 9850
|
|
|
|
NoConn ~ 3750 4900
|
|
|
|
NoConn ~ 3750 4800
|
|
|
|
NoConn ~ 3750 4700
|
|
|
|
NoConn ~ 3750 3500
|
|
|
|
NoConn ~ 3750 5200
|
2021-06-10 15:16:21 +08:00
|
|
|
$EndSCHEMATC
|