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46c84dfc20
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add remaining files
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2023-06-01 04:27:19 +08:00 |
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514b649bfc
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receiver: allow triggered alignment
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2023-05-10 00:22:40 +08:00 |
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1248a46a54
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minimal serdes communication loopback
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2023-05-08 12:43:02 +08:00 |
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b215dd1b57
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init source coding
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2023-05-07 11:13:03 +08:00 |
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e8a178a111
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multi_serdes: fix formatting
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2023-05-07 11:12:31 +08:00 |
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8bfd229bbe
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observe bit error
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2023-04-26 08:03:47 +08:00 |
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950d9ee8be
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include efc
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2023-04-26 05:08:33 +08:00 |
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ce1f669138
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handle group delay
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2023-04-25 12:17:17 +08:00 |
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f55b2593a1
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impl multi serdes tx/rx
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2023-04-25 09:41:04 +08:00 |
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24e8e9add9
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init multi loopback
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2023-04-25 07:59:04 +08:00 |
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b38a4d6b8c
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make debug mode
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2023-04-24 12:09:34 +08:00 |
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7035082d7f
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add group delay pulses
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2023-04-24 09:17:48 +08:00 |
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b73777b39f
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load optimal delay tap
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2023-04-24 07:41:58 +08:00 |
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e6902d1da5
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adjust register-wide bitslip right after slave bitslip
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2023-04-24 07:10:18 +08:00 |
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ff7c892fd6
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debug delay tap solver
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2023-04-24 06:13:05 +08:00 |
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e2a8433f83
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align master/slave pair
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2023-04-24 03:55:01 +08:00 |
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7f23de0ce8
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init
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2023-04-23 11:42:18 +08:00 |
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