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• 46c84dfc20 add remaining files master occheung 2023-06-01 04:27:19 +0800
• 514b649bfc receiver: allow triggered alignment occheung 2023-05-10 00:22:40 +0800
• 1248a46a54 minimal serdes communication loopback occheung 2023-05-08 12:43:02 +0800
• b215dd1b57 init source coding occheung 2023-05-07 11:13:03 +0800
• e8a178a111 multi_serdes: fix formatting occheung 2023-05-07 11:12:31 +0800
• 8bfd229bbe observe bit error occheung 2023-04-26 08:03:47 +0800
• 950d9ee8be include efc occheung 2023-04-26 05:08:33 +0800
• ce1f669138 handle group delay occheung 2023-04-25 12:17:17 +0800
• f55b2593a1 impl multi serdes tx/rx occheung 2023-04-25 09:41:04 +0800
• 24e8e9add9 init multi loopback occheung 2023-04-25 07:59:04 +0800
• b38a4d6b8c make debug mode occheung 2023-04-24 12:09:34 +0800
• 7035082d7f add group delay pulses occheung 2023-04-24 09:17:48 +0800
• b73777b39f load optimal delay tap occheung 2023-04-24 07:41:58 +0800
• e6902d1da5 adjust register-wide bitslip right after slave bitslip occheung 2023-04-24 07:10:18 +0800
• ff7c892fd6 debug delay tap solver occheung 2023-04-24 06:13:05 +0800
• e2a8433f83 align master/slave pair occheung 2023-04-24 03:55:01 +0800
• 7f23de0ce8 init occheung 2023-04-23 11:42:18 +0800