handle group delay
parent
f55b2593a1
commit
ce1f669138
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@ -45,54 +45,125 @@ class MultiSerDesLoopBack(Module):
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self.tx_fifo.re.eq(self.uart.tx_ack),
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]
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self.submodules.fsm = FSM(reset_state="WAIT_SELF_ALIGN")
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self.submodules.rx_fsm = FSM(reset_state="WAIT_GROUP_ALIGN")
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self.fsm.act("WAIT_SELF_ALIGN",
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If(self.rx.align_done,
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NextState("SAMPLE_RXDATA"),
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self.rx_fsm.act("WAIT_GROUP_ALIGN",
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If(self.rx.err,
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NextState("WRITE_ERR_UPPER")
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).Elif(self.rx.rxdata == 0b11111111111111111111,
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NextState("SAMPLE_RXDATA")
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),
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)
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sampled_rxdata = Signal(20)
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self.fsm.act("SAMPLE_RXDATA",
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NextValue(sampled_rxdata, self.rx.rxdata),
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NextState("WRITE_PATTERN_FIRST_UPPER"),
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)
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self.fsm.act("WRITE_PATTERN_FIRST_UPPER",
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self.rx_fsm.act("WRITE_ERR_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[8:10]),
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NextState("WRITE_PATTERN_FIRST_LOWER"),
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self.tx_fifo.din.eq(0b01010101),
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NextState("WRITE_ERR_LOWER"),
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),
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)
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self.fsm.act("WRITE_PATTERN_FIRST_LOWER",
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self.rx_fsm.act("WRITE_ERR_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[:8]),
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NextState("WRITE_PATTERN_SECOND_UPPER"),
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),
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)
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self.fsm.act("WRITE_PATTERN_SECOND_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[18:20]),
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NextState("WRITE_PATTERN_SECOND_LOWER"),
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),
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)
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self.fsm.act("WRITE_PATTERN_SECOND_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[10:18]),
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self.tx_fifo.din.eq(0b10101010),
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NextState("TERMINATE"),
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),
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)
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self.fsm.act("TERMINATE",
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sampled_rxdata = Array(Signal(20) for _ in range(5))
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sample_idx = Signal(3)
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self.rx_fsm.act("SAMPLE_RXDATA",
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If((sample_idx != 0) | (self.rx.rxdata != 0),
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If(sample_idx == 5,
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NextValue(sample_idx, 0),
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NextState("WRITE_PATTERN_FIRST_UPPER"),
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).Else(
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NextValue(sampled_rxdata[sample_idx], self.rx.rxdata),
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NextValue(sample_idx, sample_idx + 1),
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),
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),
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)
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self.rx_fsm.act("WRITE_PATTERN_FIRST_UPPER",
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If(sample_idx == 5,
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NextState("TERMINATE"),
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).Elif(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[sample_idx][8:10]),
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NextState("WRITE_PATTERN_FIRST_LOWER"),
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),
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)
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self.rx_fsm.act("WRITE_PATTERN_FIRST_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[sample_idx][:8]),
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NextState("WRITE_PATTERN_SECOND_UPPER"),
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),
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)
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self.rx_fsm.act("WRITE_PATTERN_SECOND_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[sample_idx][18:20]),
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NextState("WRITE_PATTERN_SECOND_LOWER"),
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),
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)
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self.rx_fsm.act("WRITE_PATTERN_SECOND_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[sample_idx][10:18]),
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NextValue(sample_idx, sample_idx + 1),
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NextState("WRITE_PATTERN_FIRST_UPPER"),
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),
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)
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self.rx_fsm.act("TERMINATE",
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NextState("TERMINATE"),
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)
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self.submodules.tx_fsm = FSM(reset_state="SEND_TRAINING")
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self.tx_fsm.act("SEND_TRAINING",
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self.tx.txdata.eq(0b00100001000010000100),
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If(self.rx.align_done,
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NextState("SEND_ZERO"),
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),
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)
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send_zero_duration = Signal(4)
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self.tx_fsm.act("SEND_ZERO",
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self.tx.txdata.eq(0),
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If(send_zero_duration == 0b1111,
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NextState("SEND_PULSE"),
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).Else(
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NextValue(send_zero_duration, send_zero_duration + 1),
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),
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)
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self.tx_fsm.act("SEND_PULSE",
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self.tx.txdata.eq(0b11111111111111111111),
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NextState("WAIT_GROUP_ALIGN"),
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)
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self.tx_fsm.act("WAIT_GROUP_ALIGN",
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self.tx.txdata.eq(0),
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If(self.rx.delay_done,
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NextState("SEND_ARB_DATA"),
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),
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)
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self.tx_fsm.act("SEND_ARB_DATA",
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self.tx.txdata.eq(0xDEADB),
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NextState("TERMINATE"),
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)
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self.tx_fsm.act("TERMINATE",
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self.tx.txdata.eq(0),
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NextState("TERMINATE"),
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)
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@ -1,5 +1,6 @@
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from migen import *
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from migen.genlib.misc import WaitTimer
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from migen.genlib.fifo import SyncFIFO
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from util import PriorityEncoderMSB
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@ -673,17 +674,82 @@ class MultiLineRX(Module):
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self.rxdata = Signal(20)
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# OUT: RXDATA from all channels are self-aligned
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self.align_done = Signal()
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# OUT: Group delay compensated
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self.delay_done = Signal()
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# OUT: Group delay adjustment failed
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self.err = Signal()
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channel_align_done = Signal(4)
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self.comb += self.align_done.eq(channel_align_done == 0b1111)
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buffer_outflow = Signal(4)
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self.comb += buffer_outflow.eq(0b1111)
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for idx in range(4):
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single_rx = SyncSingleRX()
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self.comb += [
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single_rx.ser_in_no_dly.eq(self.ser_in_no_dly[idx]),
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self.rxdata[5*idx:5*(idx+1)].eq(single_rx.rxdata),
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# self.rxdata[5*idx:5*(idx+1)].eq(single_rx.rxdata),
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channel_align_done[idx].eq(single_rx.align_done),
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]
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# FIFOs for handling group delay
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# Signal from each OSERDES group can have a different delay
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# So, add delay to the groups that receives the pulse early
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# Maximum delay = 8
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channel_buffer = SyncFIFO(5, 8)
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self.submodules += single_rx
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self.comb += [
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# Allow data go through the FIFO unless aligning
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# Pay the memory delay cost
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channel_buffer.we.eq(1),
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channel_buffer.re.eq(buffer_outflow[idx]),
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# Data always flow from individual RX to the rxdata port
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channel_buffer.din.eq(single_rx.rxdata),
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self.rxdata[5*idx:5*(idx+1)].eq(channel_buffer.dout),
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]
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# If at any point the FIFO fills up,
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# group delay can no longer be determined and compensated
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self.sync += [
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If(~channel_buffer.writable,
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self.err.eq(1),
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),
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]
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self.submodules += [ single_rx, channel_buffer ]
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self.submodules.fsm = FSM(reset_state="WAIT_ALIGN_DONE")
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self.fsm.act("WAIT_ALIGN_DONE",
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If(self.align_done,
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NextState("WAIT_ZERO"),
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),
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)
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self.fsm.act("WAIT_ZERO",
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If(self.rxdata == 0,
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NextState("WAIT_PULSE"),
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),
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)
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self.fsm.act("WAIT_PULSE",
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# Control outflow until all channels finds the pulse
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If(self.rxdata == 0b11111111111111111111,
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buffer_outflow.eq(0b1111),
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self.delay_done.eq(1),
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NextState("GROUP_DELAY_DONE"),
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).Else(
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buffer_outflow[0].eq(self.rxdata[ 0: 5] == 0),
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buffer_outflow[1].eq(self.rxdata[ 5:10] == 0),
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buffer_outflow[2].eq(self.rxdata[10:15] == 0),
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buffer_outflow[3].eq(self.rxdata[15:20] == 0),
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),
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)
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self.fsm.act("GROUP_DELAY_DONE",
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self.delay_done.eq(1),
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NextState("GROUP_DELAY_DONE"),
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)
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