debug delay tap solver
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@ -24,9 +24,16 @@ class SingleSerDesLoopBack(Module):
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self.submodules.tx = SingleLineTX()
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self.submodules.rx = SingleLineRX()
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# Primary adjustment to master-slave bitslip
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self.submodules.bitslip_reader = BitSlipReader()
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self.submodules.slave_aligner = SlaveAligner()
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self.submodules.post_align_reader = BitSlipReader()
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# Optimal delay solver
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self.submodules.phase_reader = PhaseReader()
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self.submodules.delay_solver = DelayOptimizer()
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# self.submodules.delay_optimizer = DelayOptimizer()
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# The actual channel
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@ -55,21 +62,21 @@ class SingleSerDesLoopBack(Module):
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# Start the reader initially
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self.bitslip_reader.start.eq(1),
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# Delay tap optimizer will start after the reader is done
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# self.delay_optimizer.start.eq(0),
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self.slave_aligner.start.eq(0),
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self.post_align_reader.start.eq(0),
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self.phase_reader.start.eq(0),
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self.delay_solver.start.eq(0),
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# RXDATA for both reader and optimzer
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self.bitslip_reader.loopback_rxdata.eq(self.rx.rxdata),
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# TODO: Reconnet
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# self.delay_optimizer.loopback_rxdata.eq(self.rx.rxdata),
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self.slave_aligner.loopback_rxdata.eq(self.rx.rxdata),
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self.post_align_reader.loopback_rxdata.eq(self.rx.rxdata),
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self.phase_reader.loopback_rxdata.eq(self.rx.rxdata),
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self.delay_solver.loopback_rxdata.eq(self.rx.rxdata),
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# Delay tap value
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# self.phase_reader.delay_tap.eq(self.rx.cnt_out),
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# TODO: Reconnet
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# self.delay_optimizer.delay_tap.eq(self.rx.cnt_out),
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self.phase_reader.delay_tap.eq(self.rx.cnt_out),
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self.delay_solver.delay_tap.eq(self.rx.cnt_out),
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# Increment control enable, such that phase_reader can
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# increment tap value after delay measurement
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@ -79,7 +86,10 @@ class SingleSerDesLoopBack(Module):
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# ).Else(
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# self.rx.ce.eq(self.phase_reader.inc_en),
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# )
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# self.rx.ce.eq(self.phase_reader.inc_en),
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self.rx.ce.eq(
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self.phase_reader.inc_en |
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self.delay_solver.inc_en
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),
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self.rx.master_bitslip.eq(
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self.bitslip_reader.bitslip |
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self.slave_aligner.master_bitslip |
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@ -93,7 +103,7 @@ class SingleSerDesLoopBack(Module):
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]
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# Show measured result on UART
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delay_tap = Signal(6)
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delay_tap_count = Signal(6)
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bitslip_count = Signal(3)
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post_align_bitslip_count = Signal(3)
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@ -109,7 +119,7 @@ class SingleSerDesLoopBack(Module):
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fsm.act("WRITE_UPPER",
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# Exist state if all results are sent
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If(bitslip_count == 5,
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NextState("FIND_OPT_DELAY"),
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NextState("START_SLAVE_ALIGNER"),
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).Elif(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.bitslip_reader.data_result[bitslip_count][8:]),
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@ -124,13 +134,13 @@ class SingleSerDesLoopBack(Module):
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NextState("WRITE_UPPER"),
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)
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fsm.act("FIND_OPT_DELAY",
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fsm.act("START_SLAVE_ALIGNER",
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self.slave_aligner.start.eq(1),
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# self.rx.ce.eq(self.delay_optimizer.inc_en),
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If(self.slave_aligner.done,
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NextState("WRITE_DONE_UPPER"),
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).Else(
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NextState("FIND_OPT_DELAY")
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NextState("START_SLAVE_ALIGNER")
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)
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)
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@ -163,7 +173,7 @@ class SingleSerDesLoopBack(Module):
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fsm.act("REWRITE_UPPER",
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# Exist state if all results are sent
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If(post_align_bitslip_count == 5,
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NextState("TERMINATE"),
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NextState("WRITE_B2P_DIVIDER_UPPER"),
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).Elif(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.post_align_reader.data_result[post_align_bitslip_count][8:]),
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@ -178,6 +188,93 @@ class SingleSerDesLoopBack(Module):
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NextState("REWRITE_UPPER"),
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)
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fsm.act("WRITE_B2P_DIVIDER_UPPER",
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self.phase_reader.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("WRITE_B2P_DIVIDER_LOWER"),
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)
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)
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fsm.act("WRITE_B2P_DIVIDER_LOWER",
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self.phase_reader.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("WAIT_PHASE_READER"),
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)
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)
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fsm.act("WAIT_PHASE_READER",
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If(self.phase_reader.done,
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NextState("WRITE_DELAY_UPPER"),
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).Else(
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NextState("WAIT_PHASE_READER"),
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)
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)
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fsm.act("WRITE_DELAY_UPPER",
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If(delay_tap_count == 32,
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NextState("DELAY_SOLVER_DIVIDER_UPPER")
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).Elif(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.phase_reader.data_result[delay_tap_count][8:]),
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NextState("WRITE_DELAY_LOWER"),
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),
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)
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fsm.act("WRITE_DELAY_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.phase_reader.data_result[delay_tap_count][:8]),
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NextValue(delay_tap_count, delay_tap_count + 1),
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NextState("WRITE_DELAY_UPPER")
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),
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)
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fsm.act("DELAY_SOLVER_DIVIDER_UPPER",
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self.delay_solver.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("DELAY_SOLVER_DIVIDER_LOWER"),
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)
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)
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fsm.act("DELAY_SOLVER_DIVIDER_LOWER",
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self.delay_solver.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("WAIT_DELAY_SOLVER"),
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)
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)
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fsm.act("WAIT_DELAY_SOLVER",
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If(self.delay_solver.done,
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NextState("WRITE_UPPER_ZERO"),
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).Else(
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NextState("WAIT_DELAY_SOLVER"),
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)
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)
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fsm.act("WRITE_UPPER_ZERO",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0x00),
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NextState("WRITE_LOWER_OPT"),
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)
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)
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fsm.act("WRITE_LOWER_OPT",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.delay_solver.opt_delay_tap),
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NextState("TERMINATE"),
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),
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)
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fsm.act("TERMINATE",
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NextState("TERMINATE"),
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)
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