Ryan Summers
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b0153b8e78
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Merge pull request #165 from vertigo-designs/feature/dma-updates
Stabilizer asynchronous batch sampling support
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2020-11-25 07:58:37 -08:00 |
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a07be010b6
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Adding comment about checking for flag pass completion
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2020-11-25 16:46:42 +01:00 |
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88da225e4b
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Adding comments about execution hanging to transfer complete waits
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2020-11-25 16:43:49 +01:00 |
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7d13627a0c
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Removing default parameter settings
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2020-11-25 16:30:06 +01:00 |
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d236ea94c4
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Updating DAC SPI structures to own HAL SPI structure for safety guarantees
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2020-11-24 17:21:14 +01:00 |
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bf8b950fe6
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Moving constants to a new file
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2020-11-24 17:09:36 +01:00 |
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720e0291f5
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Removing copy to DAC buffers, adding in-place borrow of output buffers
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2020-11-24 16:57:36 +01:00 |
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2b443f9334
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Merge branch 'master' into feature/dma-updates
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2020-11-24 16:49:11 +01:00 |
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b7c6b6d203
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Marking AXISRAM as NOLOAD
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2020-11-24 16:46:14 +01:00 |
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bors[bot]
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769cfdfb7f
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Merge #175
175: iir: document r=jordens a=jordens
Co-authored-by: Robert Jördens <rj@quartiq.de>
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2020-11-23 14:01:23 +00:00 |
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11e6688a14
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Refactoring timer channels to macros, adding safety notes
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2020-11-23 14:30:29 +01:00 |
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6808d32e0f
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iir: document
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2020-11-23 08:49:30 +01:00 |
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bors[bot]
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c91e395d12
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Merge #174
174: move iir to new dsp crate r=jordens a=matthuszagh
As mentioned [here](https://github.com/quartiq/stabilizer/pull/173#issuecomment-731751931).
Co-authored-by: Matt Huszagh <huszaghmatt@gmail.com>
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2020-11-22 18:36:24 +00:00 |
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Matt Huszagh
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d24dfb302e
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dsp crate: drop version dependency and remove boilerplate from cargo
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2020-11-22 10:32:40 -08:00 |
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Matt Huszagh
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3eb43c6b99
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move iir to new dsp crate
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2020-11-22 07:59:12 -08:00 |
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a7b6b5c796
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README: remove CI badge, add matrix link
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2020-11-16 17:36:16 +01:00 |
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04a0462aad
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README: add matrix badge
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2020-11-16 17:33:14 +01:00 |
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91809cf255
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Adding DMA support for DAC writes
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2020-11-13 10:47:44 +01:00 |
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56bcf1e0aa
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Adding sampling_timer file
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2020-11-11 18:44:28 +01:00 |
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3b953e36aa
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Adding compile-time management of TIM2 channels
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2020-11-11 18:42:34 +01:00 |
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da9ca81856
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Reverting changeset
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2020-11-11 12:12:19 +01:00 |
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3088a002c0
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Adding documentation
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2020-11-11 12:09:27 +01:00 |
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8f399ec12b
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Reverting openocd change
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2020-11-11 11:57:57 +01:00 |
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aa36446f95
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Adding updated docs for adc file
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2020-11-11 11:57:14 +01:00 |
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9cfb52308d
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Merge branch 'master' into feature/dma-updates
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2020-11-11 08:59:50 +01:00 |
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920d08c04c
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update cargosha256
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2020-11-11 15:22:47 +08:00 |
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db3bb511b4
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Merge branch 'master' into feature/dma-updates
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2020-11-10 16:55:25 +01:00 |
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Ryan Summers
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e0020f4a2a
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Merge pull request #159 from quartiq/rs/hal-update
Utilize mainline stm32h7xx-hal
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2020-11-10 16:53:00 +01:00 |
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f164a1a89e
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Update PR
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2020-11-10 15:31:19 +01:00 |
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a32ca39ca0
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Removing spaces
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2020-11-10 15:19:44 +01:00 |
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84e31ef036
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Fixing directive position
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2020-11-10 15:16:37 +01:00 |
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7b86a2bc42
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Adding comment about deprecation allowance
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2020-11-10 15:14:49 +01:00 |
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c804312e60
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Fixing deprecation warnings
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2020-11-10 15:13:57 +01:00 |
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514314dced
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Merge branch 'master' into rs/hal-update
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2020-11-10 15:13:12 +01:00 |
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bdbda8766d
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Merge pull request #164 from vertigo-designs/feature/pr-ci
Adding CI support for PRs
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2020-11-05 09:13:28 +01:00 |
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f1ee9a2af5
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Adding CI support for PRs
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2020-11-05 08:13:55 +01:00 |
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bab9fbf5ac
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Merge branch 'master' into rs/hal-update
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2020-11-05 08:09:45 +01:00 |
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2e9fdd9d4d
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Updating stm32h7xx-hal
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2020-11-05 08:06:42 +01:00 |
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5cc21cfde8
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Combining ADC + DAC ISRs
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2020-11-03 16:09:00 +01:00 |
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e95cad5bde
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Adding WIP updates
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2020-11-03 10:52:37 +01:00 |
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4e5459433e
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Formatting
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2020-11-03 09:41:45 +01:00 |
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adaca88a50
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Adding ADC/DAC modules
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2020-11-03 09:41:14 +01:00 |
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20e9b6543c
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Adding WIP updates to using DMA
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2020-11-03 09:36:03 +01:00 |
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bors[bot]
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f38c58ab53
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Merge #162
162: added gateway r=ryan-summers a=nkuh
Fixes #158
Co-authored-by: Niklas Kuhrmeyer <niklas.kuhrmeyer@ptb.de>
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2020-10-30 12:37:45 +00:00 |
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Niklas Kuhrmeyer
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2f5d26aeaa
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decreased routes_storage
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2020-10-30 13:33:59 +01:00 |
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Niklas Kuhrmeyer
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32d5e4dfe1
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format
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2020-10-30 13:32:47 +01:00 |
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Niklas Kuhrmeyer
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dfe3ac877a
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added gateway
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2020-10-30 12:16:28 +01:00 |
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f56487401c
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Adding updates for PHY support
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2020-10-28 16:14:48 +01:00 |
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11ff93e6f0
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Fixing diff
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2020-10-28 15:57:14 +01:00 |
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e36b853dc8
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Renaming clocks to ccdr
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2020-10-28 15:51:08 +01:00 |
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