Merge pull request #159 from quartiq/rs/hal-update
Utilize mainline stm32h7xx-hal
This commit is contained in:
Ryan Summers
GitHub
commit
e0020f4a2a
173
Cargo.lock
generated
173
Cargo.lock
generated
@ -10,21 +10,22 @@ dependencies = [
|
||||
|
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[[package]]
|
||||
name = "aligned"
|
||||
version = "0.3.2"
|
||||
version = "0.3.4"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "eb1ce8b3382016136ab1d31a1b5ce807144f8b7eb2d5f16b2108f0f07edceb94"
|
||||
checksum = "c19796bd8d477f1a9d4ac2465b464a8b1359474f06a96bb3cda650b4fca309bf"
|
||||
dependencies = [
|
||||
"as-slice",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "as-slice"
|
||||
version = "0.1.3"
|
||||
version = "0.1.4"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "37dfb65bc03b2bc85ee827004f14a6817e04160e3b1a28931986a666a9290e70"
|
||||
checksum = "bb4d1c23475b74e3672afa8c2be22040b8b7783ad9b461021144ed10a46bb0e6"
|
||||
dependencies = [
|
||||
"generic-array 0.12.3",
|
||||
"generic-array 0.13.2",
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"generic-array 0.14.4",
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"stable_deref_trait",
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]
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@ -41,9 +42,9 @@ dependencies = [
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[[package]]
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name = "autocfg"
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version = "1.0.0"
|
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version = "1.0.1"
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||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "f8aac770f1885fd7e387acedd76065302551364496e46b3dd00860b2f8359b9d"
|
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checksum = "cdb031dd78e28731d87d56cc8ffef4a8f36ca26c38fe2de700543e627f8a464a"
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[[package]]
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name = "bare-metal"
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@ -55,10 +56,16 @@ dependencies = [
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]
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[[package]]
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name = "bit_field"
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version = "0.10.0"
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name = "bare-metal"
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version = "1.0.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "a165d606cf084741d4ac3a28fb6e9b1eb0bd31f6cd999098cfddb0b2ab381dc0"
|
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checksum = "f8fe8f5a8a398345e52358e18ff07cc17a568fbca5c6f73873d3a62056309603"
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|
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[[package]]
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name = "bit_field"
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version = "0.10.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "dcb6dd1c2376d2e096796e234a70e17e94cc2d5d54ff8ce42b28cef1d0d359a4"
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[[package]]
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name = "bitfield"
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@ -101,12 +108,12 @@ checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"
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[[package]]
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name = "cortex-m"
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version = "0.6.3"
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version = "0.6.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "2be99930c99669a74d986f7fd2162085498b322e6daae8ef63a97cc9ac1dc73c"
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checksum = "88cdafeafba636c00c467ded7f1587210725a1adfab0c24028a7844b87738263"
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dependencies = [
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"aligned",
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"bare-metal",
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"bare-metal 0.2.5",
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"bitfield",
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"volatile-register",
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]
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@ -184,7 +191,7 @@ version = "0.2.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "fa998ce59ec9765d15216393af37a58961ddcefb14c753b4816ba2191d865fcb"
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dependencies = [
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"nb 0.1.2",
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"nb 0.1.3",
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"void",
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]
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@ -226,6 +233,16 @@ dependencies = [
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"typenum",
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]
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[[package]]
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name = "generic-array"
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version = "0.14.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "501466ecc8a30d1d3b7fc9229b122b2ce8ed6e9d9223f1138d4babb253e51817"
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dependencies = [
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"typenum",
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"version_check",
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]
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[[package]]
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name = "hash32"
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version = "0.1.1"
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@ -236,10 +253,16 @@ dependencies = [
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]
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[[package]]
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name = "heapless"
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version = "0.5.5"
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name = "hashbrown"
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version = "0.9.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "73a8a2391a3bc70b31f60e7a90daa5755a360559c0b6b9c5cfc0fee482362dc0"
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checksum = "d7afe4a420e3fe79967a00898cc1f4db7c8a49a9333a29f8a4bd76a253d5cd04"
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[[package]]
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name = "heapless"
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version = "0.5.6"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "74911a68a1658cfcfb61bc0ccfbd536e3b6e906f8c2f7883ee50157e3e2184f1"
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dependencies = [
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"as-slice",
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"generic-array 0.13.2",
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@ -250,11 +273,12 @@ dependencies = [
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[[package]]
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name = "indexmap"
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version = "1.4.0"
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version = "1.6.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "c398b2b113b55809ceb9ee3e753fcbac793f1956663f3c36549c1346015c2afe"
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checksum = "55e2e4c765aa53a0424761bf9f41aa7a6ac1efa87238f59560640e27fca028f2"
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dependencies = [
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"autocfg",
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"hashbrown",
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]
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[[package]]
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@ -282,9 +306,12 @@ dependencies = [
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[[package]]
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name = "nb"
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version = "0.1.2"
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version = "0.1.3"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "b1411551beb3c11dedfb0a90a0fa256b47d28b9ec2cdff34c25a2fa59e45dbdc"
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checksum = "801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f"
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dependencies = [
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"nb 1.0.0",
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]
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[[package]]
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name = "nb"
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@ -300,9 +327,9 @@ checksum = "de96540e0ebde571dc55c73d60ef407c653844e6f9a1e2fdbd40c07b9252d812"
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[[package]]
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name = "panic-semihosting"
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version = "0.5.3"
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version = "0.5.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "c03864ac862876c16a308f5286f4aa217f1a69ac45df87ad3cd2847f818a642c"
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checksum = "aed16eb761d0ee9161dd1319cb38c8007813b20f9720a5a682b283e7b8cdfe58"
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dependencies = [
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"cortex-m",
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"cortex-m-semihosting",
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@ -310,34 +337,15 @@ dependencies = [
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[[package]]
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name = "paste"
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version = "0.1.17"
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version = "1.0.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "026c63fe245362be0322bfec5a9656d458d13f9cfb1785d1b38458b9968e8080"
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dependencies = [
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"paste-impl",
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"proc-macro-hack",
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]
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[[package]]
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name = "paste-impl"
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version = "0.1.17"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "7b9281a268ec213237dcd2aa3c3d0f46681b04ced37c1616fd36567a9e6954b0"
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dependencies = [
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"proc-macro-hack",
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]
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[[package]]
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name = "proc-macro-hack"
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version = "0.5.16"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "7e0456befd48169b9f13ef0f0ad46d492cf9d2dbb918bcf38e01eed4ce3ec5e4"
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checksum = "ba7ae1a2180ed02ddfdb5ab70c70d596a26dd642e097bb6fe78b1bde8588ed97"
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[[package]]
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name = "proc-macro2"
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version = "1.0.18"
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version = "1.0.24"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "beae6331a816b1f65d04c45b078fd8e6c93e8071771f41b8163255bbd8d7c8fa"
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checksum = "1e0704ee1a7e00d7bb417d0770ea303c1bccbabf0ef1667dae92b5967f5f8a71"
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dependencies = [
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"unicode-xid",
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]
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@ -400,9 +408,9 @@ checksum = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3"
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[[package]]
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name = "serde"
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version = "1.0.115"
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version = "1.0.117"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "e54c9a88f2da7238af84b5101443f0c0d0a3bbdc455e34a5c9497b1903ed55d5"
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checksum = "b88fa983de7720629c9387e9f517353ed404164b1e482c970a90c1a4aaf7dc1a"
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dependencies = [
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"serde_derive",
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]
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@ -419,9 +427,9 @@ dependencies = [
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[[package]]
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name = "serde_derive"
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version = "1.0.115"
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version = "1.0.117"
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source = "registry+https://github.com/rust-lang/crates.io-index"
|
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checksum = "609feed1d0a73cc36a0182a840a9b37b4a82f0b1150369f0536a9e3f2a31dc48"
|
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checksum = "cbd1ae72adb44aab48f325a02444a5fc079349a8d804c1fc922aed3f7454c74e"
|
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dependencies = [
|
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"proc-macro2",
|
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"quote",
|
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@ -436,7 +444,6 @@ checksum = "0fe46639fd2ec79eadf8fe719f237a7a0bd4dac5d957f1ca5bbdbc1c3c39e53a"
|
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dependencies = [
|
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"bitflags",
|
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"byteorder",
|
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"log",
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"managed",
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]
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@ -461,77 +468,49 @@ dependencies = [
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"serde",
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"serde-json-core",
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"smoltcp",
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"stm32h7-ethernet",
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"stm32h7xx-hal 0.5.0 (git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/pounder-support)",
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"stm32h7xx-hal",
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]
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[[package]]
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name = "stable_deref_trait"
|
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version = "1.1.1"
|
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version = "1.2.0"
|
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source = "registry+https://github.com/rust-lang/crates.io-index"
|
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checksum = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8"
|
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checksum = "a8f112729512f8e442d81f95a8a7ddf2b7c6b8a1a6f509a95864142b30cab2d3"
|
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|
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[[package]]
|
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name = "stm32h7"
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version = "0.11.0"
|
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version = "0.12.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "e9beb5e2a223c82f263c3051bba4614aebc6e98bd40217df3cd8817c83ac7bd8"
|
||||
checksum = "7571f17d1ed7d67957d0004de6c52bd1ef5e736ed5ddc2bcecf001512269f77c"
|
||||
dependencies = [
|
||||
"bare-metal",
|
||||
"bare-metal 0.2.5",
|
||||
"cortex-m",
|
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"cortex-m-rt",
|
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"vcell",
|
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]
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|
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[[package]]
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name = "stm32h7-ethernet"
|
||||
version = "0.1.1"
|
||||
source = "git+https://github.com/quartiq/stm32h7-ethernet.git#cf9b8bb2e1b440d8ada6ac6048f48dc4ed9c269a"
|
||||
name = "stm32h7xx-hal"
|
||||
version = "0.8.0"
|
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source = "git+https://github.com/stm32-rs/stm32h7xx-hal#cbb31d0b6d0c8530437367032a600a4ff74657f7"
|
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dependencies = [
|
||||
"bare-metal 1.0.0",
|
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"cast",
|
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"cortex-m",
|
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"log",
|
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"cortex-m-rt",
|
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"embedded-hal",
|
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"nb 1.0.0",
|
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"paste",
|
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"smoltcp",
|
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"stm32h7xx-hal 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)",
|
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]
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|
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[[package]]
|
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name = "stm32h7xx-hal"
|
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version = "0.5.0"
|
||||
source = "git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/pounder-support#ff00e938f2b226211c178f26c092f36462c44404"
|
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dependencies = [
|
||||
"bare-metal",
|
||||
"cast",
|
||||
"cortex-m",
|
||||
"cortex-m-rt",
|
||||
"embedded-hal",
|
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"nb 0.1.2",
|
||||
"paste",
|
||||
"stm32h7",
|
||||
"void",
|
||||
]
|
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|
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[[package]]
|
||||
name = "stm32h7xx-hal"
|
||||
version = "0.5.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "987c66628f30012ed9a41cc738421c5caece03292c0cc8fd1e99956f122735bd"
|
||||
dependencies = [
|
||||
"bare-metal",
|
||||
"cast",
|
||||
"cortex-m",
|
||||
"cortex-m-rt",
|
||||
"embedded-hal",
|
||||
"nb 0.1.2",
|
||||
"paste",
|
||||
"stm32h7",
|
||||
"void",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "syn"
|
||||
version = "1.0.33"
|
||||
version = "1.0.48"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "e8d5d96e8cbb005d6959f119f773bfaebb5684296108fb32600c00cde305b2cd"
|
||||
checksum = "cc371affeffc477f42a221a1e4297aedcea33d47d19b61455588bd9d8f6b19ac"
|
||||
dependencies = [
|
||||
"proc-macro2",
|
||||
"quote",
|
||||
@ -546,9 +525,9 @@ checksum = "373c8a200f9e67a0c95e62a4f52fbf80c23b4381c05a17845531982fa99e6b33"
|
||||
|
||||
[[package]]
|
||||
name = "unicode-xid"
|
||||
version = "0.2.0"
|
||||
version = "0.2.1"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "826e7639553986605ec5979c7dd957c7895e93eabed50ab2ffa7f6128a75097c"
|
||||
checksum = "f7fe0bb3479651439c9112f72b6c505038574c9fbb575ed1bf3b797fa39dd564"
|
||||
|
||||
[[package]]
|
||||
name = "vcell"
|
||||
|
||||
11
Cargo.toml
11
Cargo.toml
@ -52,16 +52,9 @@ default-features = false
|
||||
[dependencies.ad9959]
|
||||
path = "ad9959"
|
||||
|
||||
[dependencies.stm32h7-ethernet]
|
||||
git = "https://github.com/quartiq/stm32h7-ethernet.git"
|
||||
branch = "master"
|
||||
features = ["stm32h743v"]
|
||||
|
||||
[dependencies.stm32h7xx-hal]
|
||||
features = ["stm32h743v", "rt", "unproven"]
|
||||
|
||||
[patch.crates-io]
|
||||
stm32h7xx-hal = { git = "https://github.com/quartiq/stm32h7xx-hal.git", branch = "feature/pounder-support" }
|
||||
features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"]
|
||||
git = "https://github.com/stm32-rs/stm32h7xx-hal"
|
||||
|
||||
[features]
|
||||
semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
|
||||
|
||||
344
src/main.rs
344
src/main.rs
@ -1,4 +1,6 @@
|
||||
#![deny(warnings)]
|
||||
// Deprecation warnings are temporarily allowed as the HAL DMA goes through updates.
|
||||
#![allow(deprecated)]
|
||||
#![allow(clippy::missing_safety_doc)]
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
@ -35,12 +37,16 @@ use stm32h7xx_hal::prelude::*;
|
||||
|
||||
use embedded_hal::digital::v2::{InputPin, OutputPin};
|
||||
|
||||
use hal::{
|
||||
dma::{DmaChannel, DmaExt, DmaInternal},
|
||||
ethernet::{self, PHY},
|
||||
rcc::rec::ResetEnable,
|
||||
};
|
||||
|
||||
use smoltcp as net;
|
||||
use smoltcp::iface::Routes;
|
||||
use smoltcp::wire::Ipv4Address;
|
||||
|
||||
use stm32h7_ethernet as ethernet;
|
||||
|
||||
use heapless::{consts::*, String};
|
||||
|
||||
#[link_section = ".sram3.eth"]
|
||||
@ -95,7 +101,7 @@ static mut NET_STORE: NetStorage = NetStorage {
|
||||
|
||||
const SCALE: f32 = ((1 << 15) - 1) as f32;
|
||||
|
||||
const SPI_START_CODE: u32 = 0x201;
|
||||
const SPI_START: u32 = 0x00;
|
||||
|
||||
// static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
|
||||
|
||||
@ -166,12 +172,12 @@ macro_rules! route_request {
|
||||
#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
|
||||
const APP: () = {
|
||||
struct Resources {
|
||||
adc0: hal::spi::Spi<hal::stm32::SPI2>,
|
||||
dac0: hal::spi::Spi<hal::stm32::SPI4>,
|
||||
adc0: hal::spi::Spi<hal::stm32::SPI2, hal::spi::Enabled, u16>,
|
||||
dac0: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
|
||||
afe0: AFE0,
|
||||
|
||||
adc1: hal::spi::Spi<hal::stm32::SPI3>,
|
||||
dac1: hal::spi::Spi<hal::stm32::SPI5>,
|
||||
adc1: hal::spi::Spi<hal::stm32::SPI3, hal::spi::Enabled, u16>,
|
||||
dac1: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
|
||||
afe1: AFE1,
|
||||
|
||||
eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
|
||||
@ -179,23 +185,14 @@ const APP: () = {
|
||||
timer: hal::timer::Timer<hal::stm32::TIM2>,
|
||||
|
||||
// Note: It appears that rustfmt generates a format that GDB cannot recognize, which
|
||||
// results in GDB breakpoints being set improperly. To debug, redefine the following
|
||||
// definition to:
|
||||
//
|
||||
// ```rust
|
||||
// net_interface: net::iface::EthernetInterface<
|
||||
// 'static,
|
||||
// 'static,
|
||||
// 'static,
|
||||
// ethernet::EthernetDMA<'static>>,
|
||||
// ```
|
||||
// results in GDB breakpoints being set improperly.
|
||||
#[rustfmt::skip]
|
||||
net_interface: net::iface::EthernetInterface<
|
||||
'static,
|
||||
'static,
|
||||
'static,
|
||||
ethernet::EthernetDMA<'static>,
|
||||
>,
|
||||
eth_mac: ethernet::EthernetMAC,
|
||||
ethernet::EthernetDMA<'static>>,
|
||||
eth_mac: ethernet::phy::LAN8742A<ethernet::EthernetMAC>,
|
||||
mac_addr: net::wire::EthernetAddress,
|
||||
|
||||
pounder: Option<pounder::PounderDevices<asm_delay::AsmDelay>>,
|
||||
@ -214,8 +211,19 @@ const APP: () = {
|
||||
let pwr = dp.PWR.constrain();
|
||||
let vos = pwr.freeze();
|
||||
|
||||
// Enable SRAM3 for the ethernet descriptor ring.
|
||||
dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
|
||||
|
||||
// Clear reset flags.
|
||||
dp.RCC.rsr.write(|w| w.rmvf().set_bit());
|
||||
|
||||
// Select the PLLs for SPI.
|
||||
dp.RCC
|
||||
.d2ccip1r
|
||||
.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
|
||||
|
||||
let rcc = dp.RCC.constrain();
|
||||
let mut clocks = rcc
|
||||
let ccdr = rcc
|
||||
.use_hse(8.mhz())
|
||||
.sysclk(400.mhz())
|
||||
.hclk(200.mhz())
|
||||
@ -226,25 +234,15 @@ const APP: () = {
|
||||
|
||||
init_log();
|
||||
|
||||
// Enable SRAM3 for the ethernet descriptor ring.
|
||||
clocks.rb.ahb2enr.modify(|_, w| w.sram3en().set_bit());
|
||||
let mut delay = hal::delay::Delay::new(cp.SYST, ccdr.clocks);
|
||||
|
||||
clocks.rb.rsr.write(|w| w.rmvf().set_bit());
|
||||
|
||||
clocks
|
||||
.rb
|
||||
.d2ccip1r
|
||||
.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
|
||||
|
||||
let mut delay = hal::delay::Delay::new(cp.SYST, clocks.clocks);
|
||||
|
||||
let gpioa = dp.GPIOA.split(&mut clocks);
|
||||
let gpiob = dp.GPIOB.split(&mut clocks);
|
||||
let gpioc = dp.GPIOC.split(&mut clocks);
|
||||
let gpiod = dp.GPIOD.split(&mut clocks);
|
||||
let gpioe = dp.GPIOE.split(&mut clocks);
|
||||
let gpiof = dp.GPIOF.split(&mut clocks);
|
||||
let gpiog = dp.GPIOG.split(&mut clocks);
|
||||
let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
|
||||
let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
|
||||
let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
|
||||
let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
|
||||
let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
|
||||
let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
|
||||
let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
|
||||
|
||||
let afe0 = {
|
||||
let a0_pin = gpiof.pf2.into_push_pull_output();
|
||||
@ -258,6 +256,9 @@ const APP: () = {
|
||||
afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
|
||||
};
|
||||
|
||||
ccdr.peripheral.DMA1.reset().enable();
|
||||
let mut dma_channels = dp.DMA1.split();
|
||||
|
||||
// Configure the SPI interfaces to the ADCs and DACs.
|
||||
let adc0_spi = {
|
||||
let spi_miso = gpiob
|
||||
@ -277,20 +278,49 @@ const APP: () = {
|
||||
polarity: hal::spi::Polarity::IdleHigh,
|
||||
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
||||
})
|
||||
.communication_mode(hal::spi::CommunicationMode::Receiver)
|
||||
.manage_cs()
|
||||
.transfer_size(1)
|
||||
.frame_size(16)
|
||||
.suspend_when_inactive()
|
||||
.cs_delay(220e-9);
|
||||
|
||||
let mut spi = dp.SPI2.spi(
|
||||
dma_channels.0.set_peripheral_address(
|
||||
&dp.SPI2.txdr as *const _ as u32,
|
||||
false,
|
||||
);
|
||||
dma_channels
|
||||
.0
|
||||
.set_memory_address(&SPI_START as *const _ as u32, false);
|
||||
dma_channels
|
||||
.0
|
||||
.set_direction(hal::dma::Direction::MemoryToPeripherial);
|
||||
dma_channels.0.set_transfer_length(1);
|
||||
dma_channels.0.cr().modify(|_, w| {
|
||||
w.circ()
|
||||
.enabled()
|
||||
.psize()
|
||||
.bits16()
|
||||
.msize()
|
||||
.bits16()
|
||||
.pfctrl()
|
||||
.dma()
|
||||
});
|
||||
dma_channels.0.dmamux().modify(|_, w| {
|
||||
w.dmareq_id()
|
||||
.variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP)
|
||||
});
|
||||
|
||||
let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi(
|
||||
(spi_sck, spi_miso, hal::spi::NoMosi),
|
||||
config,
|
||||
50.mhz(),
|
||||
&clocks,
|
||||
ccdr.peripheral.SPI2,
|
||||
&ccdr.clocks,
|
||||
);
|
||||
|
||||
spi.listen(hal::spi::Event::Eot);
|
||||
// Kick-start the SPI transaction - we will add data to the TXFIFO to read from the ADC.
|
||||
let spi_regs = unsafe { &*hal::stm32::SPI2::ptr() };
|
||||
spi_regs.cr1.modify(|_, w| w.cstart().started());
|
||||
|
||||
spi.listen(hal::spi::Event::Rxp);
|
||||
|
||||
spi
|
||||
};
|
||||
@ -313,20 +343,48 @@ const APP: () = {
|
||||
polarity: hal::spi::Polarity::IdleHigh,
|
||||
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
||||
})
|
||||
.communication_mode(hal::spi::CommunicationMode::Receiver)
|
||||
.manage_cs()
|
||||
.transfer_size(1)
|
||||
.frame_size(16)
|
||||
.suspend_when_inactive()
|
||||
.cs_delay(220e-9);
|
||||
|
||||
let mut spi = dp.SPI3.spi(
|
||||
dma_channels.1.set_peripheral_address(
|
||||
&dp.SPI3.txdr as *const _ as u32,
|
||||
false,
|
||||
);
|
||||
dma_channels
|
||||
.1
|
||||
.set_memory_address(&SPI_START as *const _ as u32, false);
|
||||
dma_channels
|
||||
.1
|
||||
.set_direction(hal::dma::Direction::MemoryToPeripherial);
|
||||
dma_channels.1.dmamux().modify(|_, w| {
|
||||
w.dmareq_id()
|
||||
.variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP)
|
||||
});
|
||||
dma_channels.1.set_transfer_length(1);
|
||||
dma_channels.1.cr().modify(|_, w| {
|
||||
w.circ()
|
||||
.enabled()
|
||||
.psize()
|
||||
.bits16()
|
||||
.msize()
|
||||
.bits16()
|
||||
.pfctrl()
|
||||
.dma()
|
||||
});
|
||||
|
||||
let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi(
|
||||
(spi_sck, spi_miso, hal::spi::NoMosi),
|
||||
config,
|
||||
50.mhz(),
|
||||
&clocks,
|
||||
ccdr.peripheral.SPI3,
|
||||
&ccdr.clocks,
|
||||
);
|
||||
|
||||
spi.listen(hal::spi::Event::Eot);
|
||||
let spi_regs = unsafe { &*hal::stm32::SPI3::ptr() };
|
||||
spi_regs.cr1.modify(|_, w| w.cstart().started());
|
||||
|
||||
spi.listen(hal::spi::Event::Rxp);
|
||||
|
||||
spi
|
||||
};
|
||||
@ -355,17 +413,17 @@ const APP: () = {
|
||||
polarity: hal::spi::Polarity::IdleHigh,
|
||||
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
||||
})
|
||||
.communication_mode(hal::spi::CommunicationMode::Transmitter)
|
||||
.manage_cs()
|
||||
.transfer_size(1)
|
||||
.frame_size(16)
|
||||
.suspend_when_inactive()
|
||||
.communication_mode(hal::spi::CommunicationMode::Transmitter)
|
||||
.swap_mosi_miso();
|
||||
|
||||
dp.SPI4.spi(
|
||||
(spi_sck, spi_miso, hal::spi::NoMosi),
|
||||
config,
|
||||
50.mhz(),
|
||||
&clocks,
|
||||
ccdr.peripheral.SPI4,
|
||||
&ccdr.clocks,
|
||||
)
|
||||
};
|
||||
|
||||
@ -387,17 +445,17 @@ const APP: () = {
|
||||
polarity: hal::spi::Polarity::IdleHigh,
|
||||
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
||||
})
|
||||
.communication_mode(hal::spi::CommunicationMode::Transmitter)
|
||||
.manage_cs()
|
||||
.transfer_size(1)
|
||||
.frame_size(16)
|
||||
.suspend_when_inactive()
|
||||
.communication_mode(hal::spi::CommunicationMode::Transmitter)
|
||||
.swap_mosi_miso();
|
||||
|
||||
dp.SPI5.spi(
|
||||
(spi_sck, spi_miso, hal::spi::NoMosi),
|
||||
config,
|
||||
50.mhz(),
|
||||
&clocks,
|
||||
ccdr.peripheral.SPI5,
|
||||
&ccdr.clocks,
|
||||
)
|
||||
};
|
||||
|
||||
@ -418,36 +476,43 @@ const APP: () = {
|
||||
let ad9959 = {
|
||||
let qspi_interface = {
|
||||
// Instantiate the QUADSPI pins and peripheral interface.
|
||||
// TODO: Place these into a pins structure that is provided to the QSPI
|
||||
// constructor.
|
||||
let _qspi_clk = gpiob
|
||||
.pb2
|
||||
.into_alternate_af9()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
let _qspi_ncs = gpioc
|
||||
.pc11
|
||||
.into_alternate_af9()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
let _qspi_io0 = gpioe
|
||||
.pe7
|
||||
.into_alternate_af10()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
let _qspi_io1 = gpioe
|
||||
.pe8
|
||||
.into_alternate_af10()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
let _qspi_io2 = gpioe
|
||||
.pe9
|
||||
.into_alternate_af10()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
let _qspi_io3 = gpioe
|
||||
.pe10
|
||||
.into_alternate_af10()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
let qspi_pins = {
|
||||
let _qspi_ncs = gpioc
|
||||
.pc11
|
||||
.into_alternate_af9()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
|
||||
let qspi =
|
||||
hal::qspi::Qspi::new(dp.QUADSPI, &mut clocks, 10.mhz())
|
||||
.unwrap();
|
||||
let clk = gpiob
|
||||
.pb2
|
||||
.into_alternate_af9()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
let io0 = gpioe
|
||||
.pe7
|
||||
.into_alternate_af10()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
let io1 = gpioe
|
||||
.pe8
|
||||
.into_alternate_af10()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
let io2 = gpioe
|
||||
.pe9
|
||||
.into_alternate_af10()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
let io3 = gpioe
|
||||
.pe10
|
||||
.into_alternate_af10()
|
||||
.set_speed(hal::gpio::Speed::VeryHigh);
|
||||
|
||||
(clk, io0, io1, io2, io3)
|
||||
};
|
||||
|
||||
let qspi = hal::qspi::Qspi::bank2(
|
||||
dp.QUADSPI,
|
||||
qspi_pins,
|
||||
10.mhz(),
|
||||
&ccdr.clocks,
|
||||
ccdr.peripheral.QSPI,
|
||||
);
|
||||
pounder::QspiInterface::new(qspi).unwrap()
|
||||
};
|
||||
|
||||
@ -455,7 +520,7 @@ const APP: () = {
|
||||
let io_update = gpiog.pg7.into_push_pull_output();
|
||||
|
||||
let asm_delay = {
|
||||
let frequency_hz = clocks.clocks.c_ck().0;
|
||||
let frequency_hz = ccdr.clocks.c_ck().0;
|
||||
asm_delay::AsmDelay::new(asm_delay::bitrate::Hertz(
|
||||
frequency_hz,
|
||||
))
|
||||
@ -476,7 +541,12 @@ const APP: () = {
|
||||
let io_expander = {
|
||||
let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
|
||||
let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
|
||||
let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), &clocks);
|
||||
let i2c1 = dp.I2C1.i2c(
|
||||
(scl, sda),
|
||||
100.khz(),
|
||||
ccdr.peripheral.I2C1,
|
||||
&ccdr.clocks,
|
||||
);
|
||||
mcp23017::MCP23017::default(i2c1).unwrap()
|
||||
};
|
||||
|
||||
@ -497,8 +567,7 @@ const APP: () = {
|
||||
let config = hal::spi::Config::new(hal::spi::Mode {
|
||||
polarity: hal::spi::Polarity::IdleHigh,
|
||||
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
||||
})
|
||||
.frame_size(8);
|
||||
});
|
||||
|
||||
// The maximum frequency of this SPI must be limited due to capacitance on the MISO
|
||||
// line causing a long RC decay.
|
||||
@ -506,22 +575,31 @@ const APP: () = {
|
||||
(spi_sck, spi_miso, spi_mosi),
|
||||
config,
|
||||
5.mhz(),
|
||||
&clocks,
|
||||
ccdr.peripheral.SPI1,
|
||||
&ccdr.clocks,
|
||||
)
|
||||
};
|
||||
|
||||
let adc1 = {
|
||||
let mut adc = dp.ADC1.adc(&mut delay, &mut clocks);
|
||||
adc.calibrate();
|
||||
let (adc1, adc2) = {
|
||||
let (mut adc1, mut adc2) = hal::adc::adc12(
|
||||
dp.ADC1,
|
||||
dp.ADC2,
|
||||
&mut delay,
|
||||
ccdr.peripheral.ADC12,
|
||||
&ccdr.clocks,
|
||||
);
|
||||
|
||||
adc.enable()
|
||||
};
|
||||
let adc1 = {
|
||||
adc1.calibrate();
|
||||
adc1.enable()
|
||||
};
|
||||
|
||||
let adc2 = {
|
||||
let mut adc = dp.ADC2.adc(&mut delay, &mut clocks);
|
||||
adc.calibrate();
|
||||
let adc2 = {
|
||||
adc2.calibrate();
|
||||
adc2.enable()
|
||||
};
|
||||
|
||||
adc.enable()
|
||||
(adc1, adc2)
|
||||
};
|
||||
|
||||
let adc1_in_p = gpiof.pf11.into_analog();
|
||||
@ -546,7 +624,12 @@ const APP: () = {
|
||||
let mut eeprom_i2c = {
|
||||
let sda = gpiof.pf0.into_alternate_af4().set_open_drain();
|
||||
let scl = gpiof.pf1.into_alternate_af4().set_open_drain();
|
||||
dp.I2C2.i2c((scl, sda), 100.khz(), &clocks)
|
||||
dp.I2C2.i2c(
|
||||
(scl, sda),
|
||||
100.khz(),
|
||||
ccdr.peripheral.I2C2,
|
||||
&ccdr.clocks,
|
||||
)
|
||||
};
|
||||
|
||||
// Configure ethernet pins.
|
||||
@ -605,15 +688,23 @@ const APP: () = {
|
||||
let (network_interface, eth_mac) = {
|
||||
// Configure the ethernet controller
|
||||
let (eth_dma, eth_mac) = unsafe {
|
||||
ethernet::ethernet_init(
|
||||
ethernet::new_unchecked(
|
||||
dp.ETHERNET_MAC,
|
||||
dp.ETHERNET_MTL,
|
||||
dp.ETHERNET_DMA,
|
||||
&mut DES_RING,
|
||||
mac_addr.clone(),
|
||||
ccdr.peripheral.ETH1MAC,
|
||||
&ccdr.clocks,
|
||||
)
|
||||
};
|
||||
|
||||
// Reset and initialize the ethernet phy.
|
||||
let mut lan8742a =
|
||||
ethernet::phy::LAN8742A::new(eth_mac.set_phy_addr(0));
|
||||
lan8742a.phy_reset();
|
||||
lan8742a.phy_init();
|
||||
|
||||
unsafe { ethernet::enable_interrupt() };
|
||||
|
||||
let store = unsafe { &mut NET_STORE };
|
||||
@ -637,7 +728,7 @@ const APP: () = {
|
||||
.routes(routes)
|
||||
.finalize();
|
||||
|
||||
(interface, eth_mac)
|
||||
(interface, lan8742a)
|
||||
};
|
||||
|
||||
cp.SCB.enable_icache();
|
||||
@ -649,28 +740,17 @@ const APP: () = {
|
||||
// Utilize the cycle counter for RTIC scheduling.
|
||||
cp.DWT.enable_cycle_counter();
|
||||
|
||||
let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, &clocks);
|
||||
dma.configure_m2p_stream(
|
||||
hal::dma::Stream::One,
|
||||
&SPI_START_CODE as *const _ as u32,
|
||||
&adc0_spi.spi.cr1 as *const _ as u32,
|
||||
hal::dma::DMAREQ_ID::TIM2_CH1,
|
||||
);
|
||||
|
||||
dma.configure_m2p_stream(
|
||||
hal::dma::Stream::Two,
|
||||
&SPI_START_CODE as *const _ as u32,
|
||||
&adc1_spi.spi.cr1 as *const _ as u32,
|
||||
hal::dma::DMAREQ_ID::TIM2_CH2,
|
||||
);
|
||||
|
||||
// Configure timer 2 to trigger conversions for the ADC
|
||||
let mut timer2 = dp.TIM2.timer(500.khz(), &mut clocks);
|
||||
timer2.configure_channel(hal::timer::Channel::One, 0.25);
|
||||
timer2.configure_channel(hal::timer::Channel::Two, 0.75);
|
||||
let timer2 =
|
||||
dp.TIM2.timer(500.khz(), ccdr.peripheral.TIM2, &ccdr.clocks);
|
||||
{
|
||||
let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() };
|
||||
t2_regs.dier.modify(|_, w| w.ude().set_bit());
|
||||
}
|
||||
|
||||
timer2.listen(hal::timer::Event::ChannelOneDma);
|
||||
timer2.listen(hal::timer::Event::ChannelTwoDma);
|
||||
// Start the SPI transfers.
|
||||
dma_channels.0.start();
|
||||
dma_channels.1.start();
|
||||
|
||||
init::LateResources {
|
||||
afe0: afe0,
|
||||
@ -693,8 +773,6 @@ const APP: () = {
|
||||
|
||||
#[task(binds = SPI3, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)]
|
||||
fn spi3(c: spi3::Context) {
|
||||
c.resources.adc1.spi.ifcr.write(|w| w.eotc().set_bit());
|
||||
|
||||
let output: u16 = {
|
||||
let a: u16 = c.resources.adc1.read().unwrap();
|
||||
let x0 = f32::from(a as i16);
|
||||
@ -703,18 +781,11 @@ const APP: () = {
|
||||
y0 as i16 as u16 ^ 0x8000
|
||||
};
|
||||
|
||||
c.resources
|
||||
.dac1
|
||||
.spi
|
||||
.ifcr
|
||||
.write(|w| w.eotc().set_bit().txtfc().set_bit());
|
||||
c.resources.dac1.send(output).unwrap();
|
||||
}
|
||||
|
||||
#[task(binds = SPI2, resources = [adc0, dac0, iir_state, iir_ch], priority = 2)]
|
||||
fn spi2(c: spi2::Context) {
|
||||
c.resources.adc0.spi.ifcr.write(|w| w.eotc().set_bit());
|
||||
|
||||
let output: u16 = {
|
||||
let a: u16 = c.resources.adc0.read().unwrap();
|
||||
let x0 = f32::from(a as i16);
|
||||
@ -723,11 +794,6 @@ const APP: () = {
|
||||
y0 as i16 as u16 ^ 0x8000
|
||||
};
|
||||
|
||||
c.resources
|
||||
.dac0
|
||||
.spi
|
||||
.ifcr
|
||||
.write(|w| w.eotc().set_bit().txtfc().set_bit());
|
||||
c.resources.dac0.send(output).unwrap();
|
||||
}
|
||||
|
||||
|
||||
@ -235,7 +235,7 @@ pub struct PounderDevices<DELAY> {
|
||||
hal::gpio::gpiog::PG7<hal::gpio::Output<hal::gpio::PushPull>>,
|
||||
>,
|
||||
mcp23017: mcp23017::MCP23017<hal::i2c::I2c<hal::stm32::I2C1>>,
|
||||
attenuator_spi: hal::spi::Spi<hal::stm32::SPI1>,
|
||||
attenuator_spi: hal::spi::Spi<hal::stm32::SPI1, hal::spi::Enabled, u8>,
|
||||
adc1: hal::adc::Adc<hal::stm32::ADC1, hal::adc::Enabled>,
|
||||
adc2: hal::adc::Adc<hal::stm32::ADC2, hal::adc::Enabled>,
|
||||
adc1_in_p: hal::gpio::gpiof::PF11<hal::gpio::Analog>,
|
||||
@ -262,7 +262,7 @@ where
|
||||
DELAY,
|
||||
hal::gpio::gpiog::PG7<hal::gpio::Output<hal::gpio::PushPull>>,
|
||||
>,
|
||||
attenuator_spi: hal::spi::Spi<hal::stm32::SPI1>,
|
||||
attenuator_spi: hal::spi::Spi<hal::stm32::SPI1, hal::spi::Enabled, u8>,
|
||||
adc1: hal::adc::Adc<hal::stm32::ADC1, hal::adc::Enabled>,
|
||||
adc2: hal::adc::Adc<hal::stm32::ADC2, hal::adc::Enabled>,
|
||||
adc1_in_p: hal::gpio::gpiof::PF11<hal::gpio::Analog>,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user