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a6d4099ed3
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lowpass: expose natural gain, add bias
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2021-02-12 11:06:59 +01:00 |
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32b7058b47
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lockin: 2nd order lowpass
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2021-02-11 23:15:32 +01:00 |
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b49f0a2eb9
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complex: log2, update bins
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2021-02-11 18:14:28 +01:00 |
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3ae0b710bc
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lowpass: reimplement better
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2021-02-11 14:30:05 +01:00 |
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30c2c2aac2
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lowpass: i32, no multiplies
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2021-02-10 11:39:19 +01:00 |
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208ba8379a
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dsp, lockin: use cascaded 1st order lowpasses
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2021-02-09 20:37:46 +01:00 |
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1b46f081c1
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better formatting
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2021-02-08 11:26:58 +01:00 |
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deed11f110
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lockin-external: simplify
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2021-02-05 18:59:22 +01:00 |
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d32378e6c4
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lockin-external: ignore timestamps related to capture overflows
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2021-02-04 12:48:58 +01:00 |
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f47ee38d31
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move sample ticks and buffer size to design parameters
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2021-02-04 12:48:25 +01:00 |
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c557348523
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core_intrinsics attr need to be in the lib crate
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2021-02-03 15:26:13 +01:00 |
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b57b666473
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Updating input capture for timers
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2021-02-03 13:03:17 +01:00 |
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e423eff0e2
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lockin-external: add doc
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2021-02-02 15:50:31 +01:00 |
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ddbfa9d988
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timestamping: docs and naming
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2021-02-02 14:34:48 +01:00 |
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854ed29b1a
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timestamp: pass overflows to the top and ignore them there
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2021-02-02 12:34:20 +01:00 |
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24a4486847
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lockin-internal: rotate samples
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2021-02-01 19:31:57 +01:00 |
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9ee60824d4
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lockin-internal: align processing with lockin-external
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2021-02-01 18:15:51 +01:00 |
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f9b5d29450
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lockin: de-nest processing flow
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2021-02-01 18:14:09 +01:00 |
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b6e22b576b
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iir: add const fn new()
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2021-02-01 17:18:10 +01:00 |
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656e3253ab
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lockin-internal: document, streamline sequence
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2021-02-01 17:09:06 +01:00 |
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65a3f839a0
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lockin: remove feed()
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2021-02-01 13:42:38 +01:00 |
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2c60103696
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dsp: accu: add, iir: rename IIRState to Vec5
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2021-02-01 12:23:47 +01:00 |
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46a7d67027
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lockin-internal: rename, adapt
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2021-01-31 19:26:11 +01:00 |
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6e1444f070
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Merge pull request #247 from quartiq/dsp-iir-benches
Dsp iir benches
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2021-01-31 19:24:56 +01:00 |
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8dc811da11
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Merge pull request #240 from vertigo-designs/feature/lockin-app-refactor
Adding internal lock-in integration demo
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2021-01-31 19:14:08 +01:00 |
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47089c267c
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dsp: align iir and iir_int, add iir micro benches
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2021-01-31 19:12:24 +01:00 |
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80055076b8
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lockin: scale output
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2021-01-31 17:41:20 +01:00 |
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82c8fa1a07
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rpll: extend tests
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2021-01-31 17:10:03 +01:00 |
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ab20d67a07
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rpll: remove redundant time tracking
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2021-01-31 13:42:15 +01:00 |
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0d1b237202
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complex: richer API
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2021-01-30 18:05:54 +01:00 |
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8b46c3c768
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Updating internal lockin demo
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2021-01-29 18:55:54 +01:00 |
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b152343aaf
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Style
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2021-01-29 11:05:46 +01:00 |
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ab7d725235
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Updating lockin demo after testing
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2021-01-29 11:01:21 +01:00 |
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1ebbe0f6d7
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Cleaning up demo
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2021-01-29 10:11:56 +01:00 |
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cf8b06be81
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Merge branch 'master' into feature/lockin-app-refactor
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2021-01-29 10:06:45 +01:00 |
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Ryan Summers
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c628b8d57a
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Update src/bin/lockin-internal-demo.rs
Co-authored-by: Robert Jördens <rj@quartiq.de>
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2021-01-29 09:55:23 +01:00 |
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c34e330663
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lockin: fmt
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2021-01-28 23:00:55 +01:00 |
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36288225b3
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rpll: extend to above-nyquist frequencies
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2021-01-28 22:21:42 +01:00 |
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1749d48ca3
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Revert "rpll: auto-align counter"
This reverts commit dbacc5293e12f712fef7bd85848e1b0bd8fde823.
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2021-01-27 09:01:07 +01:00 |
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45e7d6de3c
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rpll: auto-align counter
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2021-01-27 09:01:07 +01:00 |
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7b9fc3b2b3
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iir_int: move lowpass coefficient calculation to iirstate
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2021-01-26 18:51:20 +01:00 |
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ea7b08fc64
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rpll: refine
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2021-01-26 14:40:44 +01:00 |
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Ryan Summers
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c030b97714
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Apply suggestions from code review
Co-authored-by: Robert Jördens <rj@quartiq.de>
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2021-01-26 12:49:45 +01:00 |
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e161f49822
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Adding WIP lockin demo
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2021-01-26 12:21:44 +01:00 |
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43ff186bc6
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Merge branch 'master' into feature/lockin-app-refactor
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2021-01-26 10:53:25 +01:00 |
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7c5a74c35e
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Renaming internal lockin
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2021-01-26 10:52:35 +01:00 |
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9f9744b9e6
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rpll: implement
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2021-01-25 11:45:59 +01:00 |
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df337f85b8
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reciprocal_pll -> rpll
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2021-01-25 09:54:56 +01:00 |
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57a5c4ff9b
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make lockin a unittest, not integration test
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2021-01-22 16:04:02 +01:00 |
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d0d2c6352d
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lockin: refactor to use common lockin processing
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2021-01-22 16:00:05 +01:00 |
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