lockin: remove feed()

dsp/src/lockin.rs

@@ -1,6 +1,6 @@
 use super::{
     iir_int::{Vec5, IIR},
-    Accu, Complex,
+    Complex,
 };
 use serde::{Deserialize, Serialize};
 
@@ -41,20 +41,4 @@ impl Lockin {
             ),
         )
     }
-
-    /// Feed an iterator into the Lockin and return the latest I/Q data.
-    /// Initial stample phase and frequency (phase increment between samples)
-    /// are supplied.
-    pub fn feed<I: IntoIterator<Item = i32>>(
-        &mut self,
-        signal: I,
-        phase: i32,
-        frequency: i32,
-    ) -> Option<Complex<i32>> {
-        signal
-            .into_iter()
-            .zip(Accu::new(phase, frequency))
-            .map(|(sample, phase)| self.update(sample, phase))
-            .last()
-    }
 }

src/bin/lockin-external.rs

@@ -16,7 +16,7 @@ use stabilizer::{
     hardware, server, ADC_SAMPLE_TICKS_LOG2, SAMPLE_BUFFER_SIZE_LOG2,
 };
 
-use dsp::{iir, iir_int, lockin::Lockin, rpll::RPLL};
+use dsp::{iir, iir_int, lockin::Lockin, rpll::RPLL, Accu};
 use hardware::{
     Adc0Input, Adc1Input, Dac0Output, Dac1Output, InputStamper, AFE0, AFE1,
 };
@@ -133,13 +133,15 @@ const APP: () = {
         let sample_phase =
             phase_offset.wrapping_add(pll_phase.wrapping_mul(harmonic));
 
-        if let Some(output) = lockin.feed(
-            adc_samples[0].iter().map(|&i|
-                // Convert to signed, MSB align the ADC sample.
-                (i as i16 as i32) << 16),
-            sample_phase,
-            sample_frequency,
-        ) {
+        if let Some(output) = adc_samples[0]
+            .iter()
+            .zip(Accu::new(sample_phase, sample_frequency))
+            // Convert to signed, MSB align the ADC sample.
+            .map(|(&sample, phase)| {
+                lockin.update((sample as i16 as i32) << 16, phase)
+            })
+            .last()
+        {
             // Convert from IQ to power and phase.
             let mut power = output.abs_sqr() as _;
             let mut phase = output.arg() as _;

src/bin/lockin-internal.rs

@@ -7,7 +7,7 @@
 const DAC_SEQUENCE: [f32; 8] =
     [0.0, 0.707, 1.0, 0.707, 0.0, -0.707, -1.0, -0.707];
 
-use dsp::{iir_int, lockin::Lockin};
+use dsp::{iir_int, lockin::Lockin, Accu};
 use hardware::{Adc1Input, Dac0Output, Dac1Output, AFE0, AFE1};
 use stabilizer::hardware;
 
@@ -66,6 +66,7 @@ const APP: () = {
     /// TODO: Document
     #[task(binds=DMA1_STR4, resources=[adc1, dacs, lockin], priority=2)]
     fn process(c: process::Context) {
+        let lockin = c.resources.lockin;
         let adc_samples = c.resources.adc1.acquire_buffer();
         let dac_samples = [
             c.resources.dacs.0.acquire_buffer(),
@@ -96,13 +97,15 @@ const APP: () = {
         let sample_phase = phase_offset
             .wrapping_add((pll_phase as i32).wrapping_mul(harmonic));
 
-        if let Some(output) = c.resources.lockin.feed(
-            adc_samples.iter().map(|&i|
-                // Convert to signed, MSB align the ADC sample.
-                (i as i16 as i32) << 16),
-            sample_phase,
-            sample_frequency,
-        ) {
+        if let Some(output) = adc_samples
+            .iter()
+            .zip(Accu::new(sample_phase, sample_frequency))
+            // Convert to signed, MSB align the ADC sample.
+            .map(|(&sample, phase)| {
+                lockin.update((sample as i16 as i32) << 16, phase)
+            })
+            .last()
+        {
             // Convert from IQ to power and phase.
             let _power = output.abs_sqr();
             let phase = output.arg() >> 16;