lockin-external: add doc
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@ -83,24 +83,13 @@ const APP: () = {
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}
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}
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/// Main DSP processing routine for Stabilizer.
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/// Main DSP processing routine.
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///
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/// # Note
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/// Processing time for the DSP application code is bounded by the following constraints:
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/// See `dual-iir` for general notes on processing time and timing.
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///
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/// DSP application code starts after the ADC has generated a batch of samples and must be
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/// completed by the time the next batch of ADC samples has been acquired (plus the FIFO buffer
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/// time). If this constraint is not met, firmware will panic due to an ADC input overrun.
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///
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/// The DSP application code must also fill out the next DAC output buffer in time such that the
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/// DAC can switch to it when it has completed the current buffer. If this constraint is not met
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/// it's possible that old DAC codes will be generated on the output and the output samples will
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/// be delayed by 1 batch.
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///
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/// Because the ADC and DAC operate at the same rate, these two constraints actually implement
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/// the same time bounds, meeting one also means the other is also met.
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///
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/// TODO: document lockin
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/// This is an implementation of a externally (DI0) referenced PLL lockin on the ADC0 signal.
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/// It outputs either I/Q or power/phase on DAC0/DAC1. Data is normalized to full scale.
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/// PLL bandwidth, filter bandwidth, slope, and x/y or power/phase post-filters are available.
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#[task(binds=DMA1_STR4, resources=[adcs, dacs, iir_state, iir_ch, lockin, timestamper, pll], priority=2)]
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fn process(c: process::Context) {
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let adc_samples = [
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