Commit Graph

912 Commits

Author SHA1 Message Date
0d6b5e894c
Merge pull request #245 from vertigo-designs/rs/issue-244/gdb-fix
Removing invalid GDB command
2021-01-29 10:54:48 +01:00
d2221b8fb7 Removing invalid GDB command 2021-01-29 10:18:47 +01:00
1ebbe0f6d7 Cleaning up demo 2021-01-29 10:11:56 +01:00
cf8b06be81 Merge branch 'master' into feature/lockin-app-refactor 2021-01-29 10:06:45 +01:00
Ryan Summers
c628b8d57a
Update src/bin/lockin-internal-demo.rs
Co-authored-by: Robert Jördens <rj@quartiq.de>
2021-01-29 09:55:23 +01:00
c34e330663 lockin: fmt 2021-01-28 23:00:55 +01:00
36288225b3 rpll: extend to above-nyquist frequencies 2021-01-28 22:21:42 +01:00
702ccc231d Using custom branch of miniconf 2021-01-27 18:15:35 +01:00
1749d48ca3 Revert "rpll: auto-align counter"
This reverts commit dbacc5293e12f712fef7bd85848e1b0bd8fde823.
2021-01-27 09:01:07 +01:00
45e7d6de3c rpll: auto-align counter 2021-01-27 09:01:07 +01:00
c769bdbd4c
Merge pull request #241 from quartiq/rpll
Reciprocal PLL
2021-01-26 19:37:36 +01:00
7c1fa9695a iir lowpass: f32 is sufficient 2021-01-26 19:37:05 +01:00
73c98c947a iir_int: remove spurious note 2021-01-26 19:23:23 +01:00
2b439a0231 lockin: remove broken tests, to be rewritten 2021-01-26 19:22:02 +01:00
d1f41b3ad5 int_iir: use taylor for lowpass 2021-01-26 19:19:09 +01:00
a772ccc38a Adding WIP updates for StringSet 2021-01-26 19:14:23 +01:00
7b9fc3b2b3 iir_int: move lowpass coefficient calculation to iirstate 2021-01-26 18:51:20 +01:00
9b3a47e08b rpll: refine, simplify, document and comment 2021-01-26 18:49:31 +01:00
ea7b08fc64 rpll: refine 2021-01-26 14:40:44 +01:00
f0e7c153ba Adding WIP refactor for MQTT + settings 2021-01-26 14:28:06 +01:00
Ryan Summers
c030b97714
Apply suggestions from code review
Co-authored-by: Robert Jördens <rj@quartiq.de>
2021-01-26 12:49:45 +01:00
51085d175e Removing dead-code allowance 2021-01-26 12:23:17 +01:00
e161f49822 Adding WIP lockin demo 2021-01-26 12:21:44 +01:00
43ff186bc6 Merge branch 'master' into feature/lockin-app-refactor 2021-01-26 10:53:25 +01:00
7c5a74c35e Renaming internal lockin 2021-01-26 10:52:35 +01:00
16009c3b7e rpll: update lockin integration test 2021-01-25 12:00:47 +01:00
9f9744b9e6 rpll: implement 2021-01-25 11:45:59 +01:00
df337f85b8 reciprocal_pll -> rpll 2021-01-25 09:54:56 +01:00
659a6879f7
Merge pull request #231 from quartiq/lockin-bin
Lockin bin
2021-01-22 16:25:56 +01:00
57a5c4ff9b make lockin a unittest, not integration test 2021-01-22 16:04:02 +01:00
d0d2c6352d lockin: refactor to use common lockin processing 2021-01-22 16:00:05 +01:00
eea5033d36 dsp bench: fix 2021-01-22 11:38:38 +01:00
0cd2140668 rafactor complex, cossin, atan2 2021-01-21 16:12:59 +01:00
cb280c3303 lockin integration: reduce and refactor further 2021-01-21 15:01:17 +01:00
948e58c910 lockin: refactor Lockin 2021-01-21 14:57:44 +01:00
5af2b9c63a fmt 2021-01-20 15:34:56 +01:00
c078de05cc lockin: fix adc value conversion 2021-01-20 15:31:46 +01:00
41a907a4bf Merge branch 'master' into lockin-bin
* master:
  hitl: undo bin change to make merging easier
  build(deps): bump serde from 1.0.118 to 1.0.120
  hitl: dispatch entire github object
  build(deps): bump log from 0.4.11 to 0.4.13
2021-01-20 15:20:12 +01:00
dependabot[bot]
19a9d92220
Merge pull request #233 from quartiq/dependabot/cargo/serde-1.0.120 2021-01-20 14:12:58 +00:00
dependabot[bot]
7554a1e696
Merge pull request #224 from quartiq/dependabot/cargo/log-0.4.13 2021-01-20 14:12:42 +00:00
1cf3ce322c
Merge pull request #235 from quartiq/hitl
hitl: dispatch entire github object
2021-01-20 15:10:54 +01:00
94c4f8e6f7 hitl: undo bin change to make merging easier 2021-01-20 15:09:50 +01:00
2236e5f8ab Merge remote-tracking branch 'origin/master' into hitl
* origin/master: (34 commits)
  Reordering lib.rs
  Removing main.rs
  Adding support for multiple applications
  Fixing build
  Moving panic configuration
  Reordering
  Refactoring to support multiple apps
  Updating timer compare offsets
  reciprocal_pll: remove unneeded type cast
  revert changes in main.rs and server.rs
  dsp: add reciprocal_pll
  fix bug in which real signal component is assigned twice
  fix cargo fmt style
  use only integer iir
  remove TODO note relating ADC_BATCHES and calculate_timestamp_timer_period
  shift sin/cos before demodulation product to avoid i64
  use round up half integer rounding
  move timestamp handling into new TimestampHandler struct
  move lock-in code to main.rs
  remove debug_assert in divide_round
  ...
2021-01-20 15:08:47 +01:00
775fb79ed9 ci: update 2021-01-20 15:02:35 +01:00
d014ed0fe0 add lockin bin 2021-01-20 14:29:29 +01:00
603d6df6a4 Merge branch 'master' into lockin-bin
* master:
  Reordering lib.rs
  Removing main.rs
  Adding support for multiple applications
  Fixing build
  Moving panic configuration
  Reordering
  Refactoring to support multiple apps
2021-01-20 14:19:28 +01:00
a31c9a5a7a
Merge pull request #234 from vertigo-designs/feature/multi-app-support
Feature/multi app support
2021-01-20 14:09:47 +01:00
507e334ec5 lockin: tweak impl 2021-01-20 14:07:57 +01:00
4d0b1b5566 Reordering lib.rs 2021-01-20 13:44:53 +01:00
86355c9c5d Removing main.rs 2021-01-20 13:44:16 +01:00