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lockin: fix adc value conversion

master
Robert Jördens 2021-01-20 15:31:46 +01:00
parent 41a907a4bf
commit c078de05cc
2 changed files with 7 additions and 7 deletions
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7
dsp/tests/lockin.rs
View File

@ -59,18 +59,19 @@ impl Lockin {
self.phase.wrapping_add(phase.wrapping_mul(self.harmonic));
let mut last = Complex::default();
for s in input.iter() {
for &s in input.iter() {
let m = cossin((phase as i32).wrapping_neg());
phase = phase.wrapping_add(frequency);
let signal = (s as i32) << 16;
last = Complex(
self.iir.update(
&mut self.iir_state[0],
((*s as i64 * m.0 as i64) >> 16) as i32,
((signal as i64 * m.0 as i64) >> 32) as i32,
),
self.iir.update(
&mut self.iir_state[1],
((*s as i64 * m.1 as i64) >> 16) as i32,
((signal as i64 * m.1 as i64) >> 32) as i32,
),
);
}

7
src/bin/lockin.rs
View File

@ -140,14 +140,13 @@ const APP: () = {
let m = cossin((phase as i32).wrapping_neg());
phase = phase.wrapping_add(frequency);
let signal = (adc_samples[0][i] as i16 as i32) << 16;
let signal = Complex(
iir_lockin.update(
&mut iir_state_lockin[0],
((adc_samples[0][i] as i64 * m.0 as i64) >> 16) as _,
&mut iir_state_lockin[0], ((signal as i64 * m.0 as i64) >> 32) as _,
),
iir_lockin.update(
&mut iir_state_lockin[1],
((adc_samples[0][i] as i64 * m.1 as i64) >> 16) as _,
&mut iir_state_lockin[1], ((signal as i64 * m.1 as i64) >> 16) as _,
),
);