47089c267c
dsp: align iir and iir_int, add iir micro benches
2021-01-31 19:12:24 +01:00
8408bc5811
dsp/bench: add pll/rpll micro benches
2021-01-31 18:54:09 +01:00
43342cef91
rpll: docs
2021-01-31 18:21:47 +01:00
d281783f2e
rpll: reduce code
2021-01-31 18:10:13 +01:00
82c8fa1a07
rpll: extend tests
2021-01-31 17:10:03 +01:00
ab20d67a07
rpll: remove redundant time tracking
2021-01-31 13:42:15 +01:00
6b2d8169f0
rpll: more/cleaner tests
2021-01-31 13:25:01 +01:00
be7aad1b81
rpll: add unittest
2021-01-30 20:49:31 +01:00
0d1b237202
complex: richer API
2021-01-30 18:05:54 +01:00
36288225b3
rpll: extend to above-nyquist frequencies
2021-01-28 22:21:42 +01:00
1749d48ca3
Revert "rpll: auto-align counter"
...
This reverts commit dbacc5293e12f712fef7bd85848e1b0bd8fde823.
2021-01-27 09:01:07 +01:00
45e7d6de3c
rpll: auto-align counter
2021-01-27 09:01:07 +01:00
7c1fa9695a
iir lowpass: f32 is sufficient
2021-01-26 19:37:05 +01:00
73c98c947a
iir_int: remove spurious note
2021-01-26 19:23:23 +01:00
2b439a0231
lockin: remove broken tests, to be rewritten
2021-01-26 19:22:02 +01:00
d1f41b3ad5
int_iir: use taylor for lowpass
2021-01-26 19:19:09 +01:00
7b9fc3b2b3
iir_int: move lowpass coefficient calculation to iirstate
2021-01-26 18:51:20 +01:00
9b3a47e08b
rpll: refine, simplify, document and comment
2021-01-26 18:49:31 +01:00
ea7b08fc64
rpll: refine
2021-01-26 14:40:44 +01:00
16009c3b7e
rpll: update lockin integration test
2021-01-25 12:00:47 +01:00
9f9744b9e6
rpll: implement
2021-01-25 11:45:59 +01:00
df337f85b8
reciprocal_pll -> rpll
2021-01-25 09:54:56 +01:00
57a5c4ff9b
make lockin a unittest, not integration test
2021-01-22 16:04:02 +01:00
d0d2c6352d
lockin: refactor to use common lockin processing
2021-01-22 16:00:05 +01:00
eea5033d36
dsp bench: fix
2021-01-22 11:38:38 +01:00
0cd2140668
rafactor complex, cossin, atan2
2021-01-21 16:12:59 +01:00
cb280c3303
lockin integration: reduce and refactor further
2021-01-21 15:01:17 +01:00
948e58c910
lockin: refactor Lockin
2021-01-21 14:57:44 +01:00
c078de05cc
lockin: fix adc value conversion
2021-01-20 15:31:46 +01:00
778f4ac4d5
lockin: wrapping_neg
2021-01-19 11:30:12 +01:00
20488ea3bc
lockin: refine
2021-01-19 11:01:21 +01:00
Matt Huszagh
73ffc873cd
add lock-in integration test
2021-01-14 15:31:40 -08:00
Matt Huszagh
9a3c9afa7e
fix reciprocal_pll divide error when reference frequency is 0
2021-01-14 14:51:07 -08:00
Matt Huszagh
9f0b3eb77e
fix shift_round overflow error
2021-01-14 14:51:07 -08:00
Matt Huszagh
9697560404
reciprocal_pll: remove unneeded type cast
2021-01-13 09:08:16 -08:00
Matt Huszagh
76088efda5
dsp: add reciprocal_pll
2021-01-13 08:37:33 -08:00
Matt Huszagh
80ed715f5a
shift sin/cos before demodulation product to avoid i64
2021-01-12 16:07:04 -08:00
Matt Huszagh
41ea2ebed4
use round up half integer rounding
2021-01-12 15:59:03 -08:00
Matt Huszagh
e14aa8b613
move lock-in code to main.rs
2021-01-12 10:45:34 -08:00
Matt Huszagh
891aad3f17
remove debug_assert in divide_round
2021-01-12 07:43:28 -08:00
Matt Huszagh
31d23a3e0c
lock-in: use same method for batch_index branching in both instances
2021-01-12 07:36:56 -08:00
Matt Huszagh
bae295140d
update lock-in for integer math and PLL
2021-01-12 07:36:56 -08:00
Matt Huszagh
13543ce048
pll update input is named "x" not "input"
2021-01-04 11:14:27 -08:00
cc42c0c477
iir_int: add optimized integer iir implementation
2020-12-22 16:49:12 +01:00
8d9af70c19
trig/atan2: refine
...
* use dynamic scaling of the inputs to get accurate ratios (effectively
floating point) to maintain accuracy for small arguments
* this also allows shifting later and keep more bits
* use u32 ratio to keep one more bit
* merge the corner case unittests into the big test value list
* print rms, absolute and axis-relative angle
* simplify the correction expression to get rid of one multiplication
* use 5 bit for the correction constant and 15 bits for r
* least squares optimal correction constant, this lowers the max error
below 5e-5
2020-12-20 21:07:23 +01:00
12d5945d81
dsp/testing: simplify
2020-12-20 20:23:32 +01:00
Matt Huszagh
7e794373f4
atan2: fix output range description
2020-12-17 14:21:39 -08:00
Matt Huszagh
3125365a15
add atan2 host benchmark
2020-12-17 14:01:57 -08:00
Matt Huszagh
17cf71f22b
atan2: replace min, max with x, y
2020-12-17 11:39:32 -08:00
Matt Huszagh
9c5e68ceea
atan2: test min and max angle inputs
2020-12-17 11:34:39 -08:00
